Abstract

ABSTRACTWith the change in commuting paradigms, the demands in industries have changed accordingly. Consequently, efficient design models and related technologies have evolved as prime driving factors to this cause. In such a scenario, reversible logic design has come out as a prominent future technology which not only provides faster computing platform but also promises energy efficient designs. But it is also very evident that not only the efficient designs play a pivotal role in reliable design models but incorporation of proper testing mechanisms is very important. Further to contribute to this cause, here, in this work we introduce an efficient test vector generation method to detect all type of missing gate faults in reversible circuits. In our proposed scheme, we have explored the Boolean difference property of logic functions for designing a Boolean generator from which fault specific test vectors are computed for different fault models. The test vector generation method is composed of two phases. In first phase, a Boolean generator produces fault specific test vectors and in the second phase, we employ a repeated factoring technique over the generated test set to reduce the test size so that the testing process can be faster. We have tested our developed technique over a large spectrum of benchmarks and an improvement over existing testing works has been registered. We have achieved 71% improvements over test vector count in SMGF, 58% for MMGF and 78% for PMGF.

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