Mixing Test Set Generation for Bridging and Stuck-at Faults in Reversible Circuit

Abstract

The computation of the reversible logic circuit is gaining enough interest in the field of low-power applications and also the quantum circuit computation. In the rapid progress of synthesis design, the testing of a reversible circuit emerges area in the field of testing. In this paper, we consider the problem of testing in the reversible circuit, and in particular, generating efficient test sets for single-input stuck-at faults and bridging faults. Numerous fault models of reversible circuit have been proposed to reduce the possible faults in the circuit, many of the proposed fault models common to traditional logic. The paper proposes that for detecting all the possible input bridging faults, \((\lceil n/2 \rceil )\) numbers of test vector are required and adding only one more test vector \(((\lceil n/2 \rceil )+1)\) with an existing test set of input bridging faults can be sufficient enough for detecting another fault model, which is considered here as an input stuck-at faults. Finally, we provide our experimental results based on different reversible benchmark circuits and compared with an existing method to show that the generated test set is covered by both the fault models.