Low Power Multiplier Using Approximate Adder for Error Tolerant Applications

Abstract

In embedded applications and digital signal processing systems, multipliers are crucial components. In these applications, there is an increasing need for energy-efficient circuits. We use an approximate adder for error tolerance in the computational process to improve performance and reduce power consumption. Due to human perceptual constraints, computational errors do not significantly affect applications like image, audio, and video processing. Adiabatic logic (AL), which recycles energy, can also be used to build circuits that require less energy. In this work, we propose a carry save array multiplier employing an approximate adder based on CMOS logic and clocked CMOS adiabatic logic (CCAL) to conserve power. Additionally, using a precise full adder, multiplier parameters like average power and power delay product are calculated and compared with the multiplier. We performed simulations using 180 nm technology in Cadence Virtuoso.