Low-Power and Energy-Efficient Full Adders With Approximate Adiabatic Logic for Edge Computing

Abstract

The growing demands of data-intensive applications running on IoT edge devices require low-power and energyefficient circuits. Adiabatic logic recycles the energy and can develop energy-efficient circuits. Further, error-tolerant applications use approximate computing to reduce power consumption and area. Therefore, to investigate the benefits of approximate computing combined with adiabatic logic, we propose two adiabatic logic based approximate adders. The proposed approximate adders use the advantage of dual-rail logic to shrink the overall size and reduce energy consumption. The two proposed designs are True Sum Approximate Adder (TSAA) and True Carry-out Approximate Adder (TCAA). TSAA is approximating the Carryout based on the accurate Sum, and TCAA is approximating the Sum based on the accurate Carryout. We performed simulations using 45nm technology in Cadence Spectre. Comparing with CMOS based accurate mirror adder (AMA) at 100 MHz, a power-saving of 83.26% and energy saving of 66.54% in PFAL based TSAA (PFAL: Positive Feedback Adiabatic Logic) is achieved. Further, we achieved a power saving of 87.22% and an energy saving of 74.43% in PFAL based TCAA compared to CMOS based accurate mirror adder (AMA). It is illustrated that PFAL based TCAA consumes 24.0% less power and energy per cycle compared to PFAL based TSAA.