Adiabatic flip-flops and sequential circuit design using novel resettable adiabatic buffers

Abstract

We propose novel resettable adiabatic buffers for five adiabatic logic families namely; Efficient Adiabatic Charge Recovery Logic (EACRL), Improved Efficient Charge Recovery Logic (IECRL), Positive Feedback Adiabatic Logic (PFAL), Complementary Pass-transistor Adiabatic Logic (CPAL) and Clocked Adiabatic Logic (CAL). We present the design of resettable flip-flops using the proposed buffers. The proposed flip-flops alleviate the problem of increased energy and area consumption incurred by the existing mux-based resettable flip-flops. We then design the 3-bit up-down counters and extended our comparison beyond energy dissipation using the above five adiabatic logic families. PFAL based sequential circuit designs gives the best performance trade-offs in terms of complexity, energy, speed and area compared to the other adiabatic designs.