Test pattern generation using thermometer code counter in TPC technique for BIST implementation

Abstract

This paper introduces a newly pattern generation with Test-Per-Clock technique for Built-In-Self-Test implementation. This proposed test vector generation generates Multiple Single Input Change vectors. Each pattern enforced in SIC vector as scan chain. To generate minimal transition sequence of test patterns, a scalable SIC counter and Thermometer Code Counter implemented. The proposed Multiple SIC vector generator is adaptable to both Test-Per-Scan, Test-Per-Clock techniques. This method developed a theory to evaluate MSIC scheme. Survey outcome demonstrates that, applying Multiple SIC test patterns on ISCAS C432 benchmark reduces the power consumption due to uniform distribution and lesser transition generated test patterns.