Generation of Reduced Test Vectors for Multiple Stuck at Faults using Genetic Algorithm

Abstract

As seen in the fabrication of circuits faults free circuits are difficult to obtain, as the manufacturing process is narrowing down, hence finding faults is very essential at the design level to obtain fault free circuits. As seen many of circuits have single and multiple faults, as known many research has been carried out to generate test pattern set that detect MSA faults, here the proposed ATPG method makes use of test patterns of single stuck at faults to identify MSA faults. This paper implements a method for multiple faults, generated test patterns for multiple faults has proved to be efficient by adapting a complex method of the order 3n-1 for ‘n’ lines reduced test pattern sets were obtained. This method overcomes the limitations of continuous searching algorithms, as the initial value of population size was randomly set to produce test vectors for MSA faults. The CPU processing time is very less compared to other ATPG techniques. To understand the working of the proposed methodology, we have performed an analysis by considering the ISCAS Benchmark circuits, to which the proposed ATPG method is applied, which gives the complete test vector (pattern) generation for MSA faults in the limited interval of runtime which also covers the test pattern sets for single faults.