Ternary Content Addressable Memory Research Articles

Algorithmic TCAMs: Implementing Packet Classification Algorithms in Hardware

The adoption of cloud computing and the deployment of new services require more and more computing and networking resources in large data centers. In particular, there is a need for faster, rich featured switches. Today, switching integrated circuits can handle more than 50 Tb/s and are expected to reach 100 Tb/s next year. This trend is likely to continue, approaching petabit capacities in a few years. At the same time, switches need to support more advanced packet classification features. This poses many challenges to the designers of switching integrated circuits, creating a need for innovations to move forward. One of those challenges is to support programmable packet classification with large rulesets at wire speed using limited silicon footprint. Unfortunately, traditional solutions like ternary content addressable memories (TCAMs) have high cost in area and power, and therefore are not a viable option for large on-chip rulesets, so new alternatives are needed. In the last two decades, researchers have extensively studied the problem of packet classification, proposing many algorithms based on standard memories, mostly targeting software implementations. These packet classification algorithms could be a solution to enable large on-chip classification rulesets using standard memories. However, porting the standard packet classification algorithms to a hardware implementation is not a trivial task, due to the different requirements and the different kinds of memory and computing resources available on application-specific integrated circuit (ASIC) switching chips. This article describes a packet classification design tailored for high-speed switching integrated circuits, which is currently used in the NVIDIA® Mellanox® Spectrum® switching ASIC product line, illustrating how to solve the mismatch between the usual software-based classification algorithms and the specific requirements of a hardware implementation.

VLSI implementation of low-power and area efficient parallel memory allocation with EC-TCAM

VLSI-based programmable devices support improved software-based reconfigurability and hardware performance, which are adopted as developing platforms to implement complex systems, i.e., signal processors, software-defined networks, and image processing applications. Parallel memory allocation (PMA) among various resources plays a crucial role in meeting the high-performance requirements in these applications. The conventional methods were implemented with static random-access memory (SRAM) prototypes, but they failed to meet the maximum data transfer speed. This article focuses on the implementation of error-correctable ternary content-addressable memory (EC-TCAM)-based parallel memory allocation (PMA) systems with error-resilient properties, which can be capable of detecting and correcting errors during the parallel data allocation. Further, the priority circuit is used to generate the different levels of priorities, which helps to transfer the data between master and slave devices and vice-versa. Here, the synchronization issues generated during parallel reading and writing operations are minimized using priority circuit-controlled crossbar switching. The simulation results show the proposed EC-TCAM based PMA resulted in superior performance as compared to the conventional approaches in terms of hardware resource utilization parameters such as slice registers, look up tables (LUTs), LUT-flip-flops (LUT-FFs), delay, and power consumption. Finally, the proposed method utilized 310 slice registers, 235 LUTs, 156 LUT-FFs, 0.793ns of path delay, and 0.065 W of power.

A Highly Compact Nonvolatile Ternary Content Addressable Memory (TCAM) With Ultralow Power and 200-ps Search Operation

In this work, we developed a nonvolatile ternary content addressable memory (TCAM) with a cell size of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0.01~\mu \text{m}^{{2}}$ </tex-math></inline-formula> utilizing the Ge-based memory diode (MD), which has the most area-efficient TCAM design reported. The MDs have a high current ratio between ON and OFF states and a large rectifying ratio, showing the potential usage in large-dimension TCAM arrays. Besides, the functionality of parallel search was demonstrated with a 2-bit MD-TCAM array by experiment, and the electrical characterization showed expected results. With the help of the sub-ns ultrafast measurement system, it is confirmed that the search energy of MD-TCAM could reach as low as 1.0 fJ/bit/mismatch, and one search operation can be performed within 200 ps. Furthermore, the circuit-level simulation results verified that the MD-TCAM developed in this study shows good performance in 128-bit parallel searching, which is promising for the ultrafast and low-power data search applications in the coming IoT era.

Compiling All-Digital-Embedded Content Addressable Memories on Chip for Edge Application

A spectrum of emerging applications, including edge artificial intelligence, advocates the precompute-and-search scheme with embedded small-size content addressable memory (CAM) for its hardware efficiency instead of repetitive arithmetic operations. However, the integration of the CAM macros that are conventionally implemented with full custom analog circuits renders design-space exploration and optimization to be difficult at system level. As an alternative, a complete design flow for compiling ternary CAM on chip using foundry-supplied digital standard cells is introduced in this article. Based on the novel CAM architecture and logic design, we leverage guided placement and routing with mainstream EDA tools for exploiting the inherent structure regularity of CAM-cell arrays in the layout. An analytical model is also presented, which allows us for a systematic investigation on the energy reduction by adapting our design to various presearch structures. Validated on a postlayout <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$32{\times }64$ </tex-math></inline-formula> ternary CAM in 28 nm, our parallel-matching scheme performs at 2.6 GHz with 0.42 fJ/bit/search, and the (8-bit) presearch scheme achieves 0.19 fJ/bit/search at 1.1 GHz, both under the 0.9-V supply voltage. In addition to flexibility for tradeoffs between the search throughput and energy, our all-digital CAM design enables voltage scaling aggressively down to 0.45 V with a minimum energy consumption of 0.06 fJ/bit/search at 50 MHz.

High-Speed Memristive Ternary Content Addressable Memory

This article presents an ultra-high-speed memristor-based non-volatile Ternary Content Addressable Memory (TCAM) for use in real-time and big-data applications that require low power dissipation and fast data retrieval. It proposes a novel memristive TCAM (MTCAM) cell using memristors as a bit storage device along with an ultra-fast match line sense amplifier to minimize search time. SPICE simulation on 45 nm technology show that the search delay on a 144-bit proposed MTCAM at a supply voltage of 1 V and a sense margin of 140 mV is 175 ps with per bit search energy of 1.2 fJ. It is 1.12× times faster and dissipates 67 percent less search energy per bit than the fastest existing 144-bit MTCAM design.

In-Memory Search With Phase Change Device-Based Ternary Content Addressable Memory

Here, we proposed an in-memory search prototype based on phase change memory (PCM). First, using the PCM, a highly compact (8F <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> ) and low-energy (0.3 fJ/bit/search) nonvolatile ternary addressable memory (TCAM) is demonstrated and achieved a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$6.6\times $ </tex-math></inline-formula> energy saving and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$50\times $ </tex-math></inline-formula> cell area saving over the 16T SRAM-TCAM. Thanks to the non-volatility and massive parallelism of the PCM TCAM to computing Hamming distance, the frequent memory access is alleviated, enabling search operation in situ. The prototype shows a high throughput of 256 GB/s in data deduplication application, obtaining more than <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$250\times $ </tex-math></inline-formula> energy saving and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$42\times $ </tex-math></inline-formula> improvement in throughput over CPU. Our study provides a low-area-overhead, low-energy, and high-throughput solution for the storage system to perform search in situ.

Layered methods for updating AIoT-compatible TCAMS in B5G-enabled WSNs

Classification is a fundamental processing task in advanced network systems. This technique is exploited in 5G/6G wireless sensors networks where flow-based processing of the internet packets is highly demanded by intelligent applications that analyze big volumes of data in a limited time. In this process, the input packets are classified into specific streams by matching to a set of filters. The ternary content-addressable memory (TCAM) is used in hardware implementation of internet packets. However, due to the parallel search capabilities, this memory leads to an increase in the speed and drop of hardware bundles compared to other types of software bundles, but with the increase in the number of rules stored in its layers, the power required for searching, inserting and eliminating increases. Various architectures have been proposed to solve this problem, but none of them has proposed a plan to reduce power consumption while updating the rules in the TCAM memory. In this paper, two algorithms are presented for reducing power consumption during TCAM memory upgrades. The key idea in the proposed algorithms is the reduction in the search range as well as the number of displacements while inserting and deleting rules in TCAM. Implementation and evaluation of proposed methods represent a reduction of more than 50% of the number of visits to TCAM in both proposed algorithms, as well as reducing the update time in the second proposed algorithm compared to the first proposed algorithm which confirms the efficiency of both methods.

Optimal Weighted Load Balancing in TCAMs

Traffic splitting is a required functionality in networks, for example for load balancing over multiple paths or among different servers. The capacities of the servers determine the partition by which traffic should be split. A recent approach implements traffic splitting within the ternary content addressable memory (TCAM), which is often available in switches. It is important to reduce the amount of memory allocated for this task since TCAMs are power consuming and are often also required for other tasks such as classification and routing. Previous work showed how to compute the smallest prefix-matching TCAM necessary to implement a given partition exactly. In this paper we solve the more practical case, where at most <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$n$ </tex-math></inline-formula> prefix-matching TCAM rules are available, restricting the ability to implement exactly the desired partition. We give simple and efficient algorithms to find <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$n$ </tex-math></inline-formula> rules that generate a partition closest in <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$L_\infty $ </tex-math></inline-formula> to the desired one. We do the same for a one-sided version of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$L_\infty $ </tex-math></inline-formula> which equals to the maximum overload on a server and for a relative version of it. We use our algorithms to evaluate how the expected error changes as a function of the number of rules, the number of servers, and the width of the TCAM.

Gate All around CNTFET based Ternary Content Addressable Memory

This paper proposes a design of gate all around CNTFET based ternary content addressable memory (TCAM). TCAM cell is designed and simulated in HSPICE using top gated CNTFET (TG-CNTFET) & gate all around CNTTFET (GAA-CNTFET). Dual chirality technique is used to design TCAM cell i.e. different chirality for n-type CNTFET & p-type CNTFET which utilizes different threshold voltages and hence improve the performance. Comparative analysis has been done for various parameters viz. Static noise margin (SNM), delay, power and power delay product (PDP). It has been found that GAA-CNTFET based TCAM gives better SNM and power as compared to TG-CNTFET based TCAM, however TG-CNTFET based TCAM gives less delay. However overall PDP is less in GAA-CNTFET which make is suitable for circuit applications as compared to TG-CNTFET.

Comp-TCAM: An Adaptable Composite Ternary Content-Addressable Memory on FPGAs

Field-programmable gate arrays (FPGAs) having software-like reconfigurability and hardware-like performance are adopted as developing platforms to implement complex systems, i.e., software-defined networks (SDNs). Ternary content-addressable memory (TCAM) is not present in modern FPGA, but rather it is used as a softcore where needed. The hardware structure of an FPGA is flexible but rigid; the elemental structure is fixed and can be used in a limited number of ways. Existing FPGA-based TCAMs exhaust one particular type of memory when a large size is implemented, resulting in a shortage of memory for the rest of the system. Our proposed architecture uses only those memory elements of FPGA that are redundant and not used by other parts. In this letter, the proposed architecture, comp-TCAM, combines both block RAM (BRAM) and lookup table RAM (LUTRAM) to implement the TCAM architecture; that eliminates the dependency on the type of memory and is adaptable to the requirement of the system. Evaluation results show the feasibility, scalability, and effectiveness of the proposed TCAM architecture compared to the existing TCAM architectures. The hardware resource utilization on Xilinx VIrtex-7 FPGA is reduced by 41.6% compared to state-of-the-art FPGA-based TCAM with no harm to the system’s performance providing a throughput of 21.06 Gbits/s.

A FeFET-Based Hybrid Memory Accessible by Content and by Address

Emerging nonvolatile memory technologies are attracting interest from the system design level to implement alternatives to conventional von-Neumann computing architectures. In particular, the hafnium oxide-based ferroelectric (FE) memory technology is fully CMOS-compatible and has already been used for logic-in-memory architectures or compact ternary content addressable memory (TCAM) cells. These enable the tight combination of different functionalities in the same circuit to reduce implementation area and energy consumption. In this article, we propose a new hybrid memory circuit that combines TCAM and normal memory capability: the Ternary Content addressable and MEMory (TC-MEM). A 1-bit TC-MEM circuit is proposed and discussed in detail, both as a concept and through its implementation in a 28-nm ferroelectric field-effect transistor (FeFET) technology. Measurement results demonstrate the circuit functionality. We also discuss how to scale it to multibit circuits, as well as its use both as a TCAM and as a normal memory allowing the implementation of reversible functions using one memory table instead of two memory tables, and in-memory-computing concepts.

GP3D: 3D NAND Based In-Memory Graph Processing Accelerator

In this work, we proposed GP3D: 3D NAND based processing-in-memory (PIM) accelerator for highly parallel and energy efficient graph processing. Although graph processing algorithms give informative and useful features from the real world graphs, innate randomness of the graph data pattern incurs inefficient processing in conventional computing architectures. Some previous works on nonvolatile memory (NVM) based PIM architecture have been proposed with vector-matrix multiplication (VMM) in memory array, but the limited memory capacity of the architecture causes frequent write operations on memory cells. Our GP3D architecture is based on the standard 3D NAND array structure without any structural changes which can utilize the ultra-high density of 3D NAND to store the large scale graphs in a single die. VMM operations on 3D NAND array enables efficient processing of PageRank algorithm, one of the representative algorithms of graph processing. To process the graphs with compressed format without conversion to the dense format, we exploited ternary content addressable memory (TCAM) function on 3D NAND. GP3D can eliminate the data loading burdens from storage device to memory which gives significant enhancement of the latency and energy efficiency. Evaluated by custom designed graph processing simulator, GP3D showed 30&#x2013;61 times boosted speed and 18&#x2013;64 times better energy efficiency over the GPU based system for various graph datasets.

TCAM Network Memory Error Detection and Correction Method

Ternary content addressable memories (TCAMs) are widelyused in network devices to implement packet classification. They are used, for example, for packet forwarding, for security, and to implement software-defined networks (SDNs). TCAMs are commonly implemented as standalone devices or as an intellectual property block that is integrated on networking application-specific integrated circuits. On the other hand, field-programmable gate arrays (FPGAs) do not include TCAM blocks. However, the flexibility of FPGAs makes them attractive for SDN implementations, and most FPGA vendors provide development kits for SDN. Those need to support TCAM functionality and, therefore, there is a need to emulate TCAMs using the logic blocks available in the FPGA. In recent years, a number of schemes to emulate TCAMs on FPGAs have been proposed. Some of them take advantage of the large number of memory blocks available inside modern FPGAs to use them to implement TCAMs. A problem when using memories is that they can be affected by soft errors that corrupt the stored bits. The memories can be protected with a parity check to detect errors or with an error correction code to correct them, but this requires additional memory bits per word. In this brief, the protection of the memories used to emulate TCAMs is considered. In particular, it is shown that by exploiting the fact that only a subset of the possible memory contents are valid, most single-bit errors can be corrected when the memories are protected with a parity bit.

FPGA implementation of hybrid recursive reversable box filter-based fast adaptive bilateral filter for image denoising

A Bilateral filter (BF) is a kind of edge-preserving filter, which is mostly used in computer vision, computational photography, and image processing applications. Recently, Reversible Logic Gates (RLG) technology has emerged as an attractive area in the field of field-programmable gate array (FPGA) based implementations. The RLG technology consumes less Quantum Cost (QC) as compared to conventional CMOS-based logic gates. As a result, this paper proposed an FPGA implementation of a hybrid recursive reversible box filter (HRRBF)-based fast adaptive bilateral filter (FABF) using RLG technology with joint geometric and photometric weight calculation and kernel result calculation operations. The RLGs are used to develop the reversable modified carry select adder (RMCSA), reversable adder subtractor (RAS), and multiplier, which significantly improves the speed and reduces the execution time, area, power, and delay as compared to the basic methods. In addition, ternary content addressable memory (TCAM) is used as the main memory to improve the speed of filtering. Obtained hardware and simulation results show that proposed RLG-based HRRBF-FABF results in enhanced performance as compared to state-of-the-art architectures. In addition, the image denoising application was also implemented with the proposed RLG-based HRRBF-FABF and achieved structural similarity (SSIM) index of 0.999 and peak signal-to-noise ratio (PSNR) of 78.348 dB. The simulation results showed that the proposed method resulted in better denoising performance as compared to conventional filtering approaches.

An efficient packet parser architecture for software-defined 5G networks

Software-defined networks (SDN) has emerged with the capability to program in order to enhance flexibility, management, and testing of new ideas in the next generation of networks by removing current network limitations. Network virtualization and functionalization are critical elements supporting the delivery of future network services, especially in 5G networks. With the integration of virtualization and functionalization, network resources can be provisioned on-demand, and network service functions can be composed and chained dynamically to cater to various requirements. 5G networks are expected to rely heavily on SDN, which has been widely applied in core network design. To have a software-defined 5G network, not only is new spectrum and interface needed from SDN, but also a programmable and efficient hardware infrastructure is required. Admittedly, hardware components and infrastructure play an important role in supporting 5G networks. In other words, the software-defined 5G network data plane must have the required flexibility and programmability to support upcoming needs and technologies. Technological solutions need to respond to actual requests in infrastructure. Packet parsers in the data plane of software-defined 5G networks are one of the most important components because of the variation in the type of network headers and protocols. Each SDN switch needs to identify headers for processing input packets in the data plane, where the packet parser operates. Multiple implementations of packet parsers have been done on different substrates that occupy large hardware resources and areas on chip. However, they are not suitable for software-defined 5G networks. Certain architectures have been presented for packet parsing, aimed at accelerating the process of header parsing, however no attention has been paid toward reducing the area and the volume of the needed hardware resources and programmability in the data plane. This paper presents a new and efficient architecture for packet parsers on Field Programmable Gate Arrays (FPGA), called Efficient FPGA Packet Parser (EFPP) in a designed software-defined 5G network. This architecture emphasizes the removal of Ternary Content Addressable Memory (TCAM) to decrease hardware resources and efficiency in the data plane. Moreover, this architecture uses the chip’s processing speed and reconfiguration capabilities to support new protocols and network headers while maintaining flexibilities on software-defined 5G networks. EFPP is applied to chips on FPGA Xilinx ZedBoard Zynq, and the resources consumed around 7.5% LookUp Table, 1.9% Flip-Flops, and 5.8% of the memory. EFPP was also more area efficient. According to our results, EFPP would reduce the area and volume of hardware compared to other peer works.

Dynamic Flow Reduction Scheme Using Two Tags Multi protocol Label Switching (MPLS) in Software Define Network

Software-Defined Networking (SDN) is a technique that breaks the vertical integration of networks by separating the networks’ control logic from the underlying routers and switches that forward the traffic. The performance of SDN network nodes may be degraded due to flow entries that are frequently updated and stored in the network elements. The control plane is flooded by the configuration messages thereby resulting in a trade-off between the number of configuration messages and number of permanent flow entries in the network.The focus of the study is to develop a scheme that will reduce the number of flow entries of IPv6 packets using two multiprotocol label switching tags in Software Defined Networks. An experimental testbed was developed using openvswitch, Ryu controller, OpenFlow version 1.3, IPERF3 and Wireshark. A Mininet kernel was built on Ubuntu Linux 18.04.1 operating system. The IPv6 Hybrid Permanent Flow (HPF) scheme and Non-Permanent Flow (NPF) was used to reduce the number of permanent flow entries and the number of configuration messages from the controller to the Ternary Content Addressable Memory (TCAM) of the Openswitch.The Result shows that IPv6 HPF scheme had a reduction of 63% as against NPF in the network for the dependency of switch per region while 33% reduction in flow entries of the network for the dependency of host per switch. The result can be used by Internet Service Providers (ISPs) for real-time network flow that will provide handling of an unpredictable surge of big-data transmission across network backbone.

A skyrmion content-addressable cell for skyrmion magnetic memories

Content-addressable memories (CAMs) allow searching a pattern, processing in parallel all the data stored. Beyond-CMOS technologies can provide new opportunities to improve CAM memories implementations both at the device and architectural level. In this article, we propose a ternary content-addressable memory cell based on skyrmion technology. The proposed memory cell is based on skyrmion racetrack memory. The cell is able to signal if the bit contained in the cell in form of skyrmion corresponds to an electrical input, the target of the search operation. The proposed design, verified by means of micromagnetic simulations, has an area of 0.054 μm2 and can perform a search operation in 3.3 ns with an energy of 10.5 fJ. The operation performed is non-destructive and does not require conversion between the magnetic and the electronic domains. For this reason, the designed cell has the potential to be used as a basic block for non-volatile CAM memories. Here, we propose also a layout structure to implement a CAM memory employing the proposed cell. This structure allows to achieve memory density comparable to traditional racetrack memories and execute at the same time CAM operations.

Content-Addressable Memory System Using a Nanoelectromechanical Memory Switch

Content-addressable memory (CAM) performs a parallel search operation by comparing the search data with all content stored in memory during a single cycle, instead of finding the data using an address. Conventional CAM designs use a dynamic CMOS architecture for high matching speed and high density; however, such implementations require the use of system clocks, and thus, suffer from timing violations and design limitations, such as charge sharing. In this paper, we propose a static-based architecture for a low-power, high-speed binary CAM (BCAM) and ternary CAM (TCAM), using a nanoelectromechanical (NEM) memory switch for nonvolatile data storage. We designed the proposed CAM architectures on a 65 nm process node with a 1.2 V operating voltage. The results of the layout simulation show that the proposed design has up to 23% less propagation delay, three times less matching power, and 9.4 times less area than a conventional design.

A modular approach to design ternary content addressable memory architecture in quantum dot cellular automata

A modular approach to design ternary content addressable memory architecture in quantum dot cellular automata

SDN-Based Traffic Matrix Estimation in Data Center Networks through Large Size Flow Identification

Software defined networking (SDN) with separated control plane and data plane brings new opportunities for traffic measurement in data center networks. However, in the SDN-enabled switches, available TCAM (Ternary Content Addressable Memory) resources for traffic measurement are limited. Thus, it is necessary to utilize traffic matrix (TM) estimation to derive a hybrid network monitoring scheme through combining the partial direct measurement offered by SDN with some inference techniques. Although large size flows play an important role in improving TM estimation accuracy, directly monitoring each flow and finding out large size flows consume massive channel bandwidth resource between control plane and data plane. Therefore, in this paper, we identify large size flows from multiple historical TMs instead of monitoring each flow. First, we analyze multiple historical TMs and observe that origin-to-destination (OD) pair whose flow size is selected as large size flow at last time slot is most likely to be selected for per-flow monitoring at next time slot, so these OD pairs are identified by gradient boosting machine and are directly regarded as sampled OD pairs in order to reduce resource consumption. Then, we propose a greedy heuristic algorithm to solve SDN-enabled switch selection problem to best utilize the TCAM resources and guarantee that most of sampled OD pairs are measured in the flow table. We also present a source node prefix tree based bit merging aggregation (SPTBMA) scheme to design feasible forwarding rules to be inserted in TCAM of SDN-enabled switches and reserve more TCAM space for sampled OD pairs. Finally, the experimental results based on real traffic dataset demonstrate that our proposed scheme outperforms the existing algorithms in terms of improving TM estimation accuracy and overcoming limitation of TCAM resources.