VLSI implementation of low-power and area efficient parallel memory allocation with EC-TCAM

Abstract

VLSI-based programmable devices support improved software-based reconfigurability and hardware performance, which are adopted as developing platforms to implement complex systems, i.e., signal processors, software-defined networks, and image processing applications. Parallel memory allocation (PMA) among various resources plays a crucial role in meeting the high-performance requirements in these applications. The conventional methods were implemented with static random-access memory (SRAM) prototypes, but they failed to meet the maximum data transfer speed. This article focuses on the implementation of error-correctable ternary content-addressable memory (EC-TCAM)-based parallel memory allocation (PMA) systems with error-resilient properties, which can be capable of detecting and correcting errors during the parallel data allocation. Further, the priority circuit is used to generate the different levels of priorities, which helps to transfer the data between master and slave devices and vice-versa. Here, the synchronization issues generated during parallel reading and writing operations are minimized using priority circuit-controlled crossbar switching. The simulation results show the proposed EC-TCAM based PMA resulted in superior performance as compared to the conventional approaches in terms of hardware resource utilization parameters such as slice registers, look up tables (LUTs), LUT-flip-flops (LUT-FFs), delay, and power consumption. Finally, the proposed method utilized 310 slice registers, 235 LUTs, 156 LUT-FFs, 0.793ns of path delay, and 0.065 W of power.