FPGA implementation of hybrid recursive reversable box filter-based fast adaptive bilateral filter for image denoising

Abstract

A Bilateral filter (BF) is a kind of edge-preserving filter, which is mostly used in computer vision, computational photography, and image processing applications. Recently, Reversible Logic Gates (RLG) technology has emerged as an attractive area in the field of field-programmable gate array (FPGA) based implementations. The RLG technology consumes less Quantum Cost (QC) as compared to conventional CMOS-based logic gates. As a result, this paper proposed an FPGA implementation of a hybrid recursive reversible box filter (HRRBF)-based fast adaptive bilateral filter (FABF) using RLG technology with joint geometric and photometric weight calculation and kernel result calculation operations. The RLGs are used to develop the reversable modified carry select adder (RMCSA), reversable adder subtractor (RAS), and multiplier, which significantly improves the speed and reduces the execution time, area, power, and delay as compared to the basic methods. In addition, ternary content addressable memory (TCAM) is used as the main memory to improve the speed of filtering. Obtained hardware and simulation results show that proposed RLG-based HRRBF-FABF results in enhanced performance as compared to state-of-the-art architectures. In addition, the image denoising application was also implemented with the proposed RLG-based HRRBF-FABF and achieved structural similarity (SSIM) index of 0.999 and peak signal-to-noise ratio (PSNR) of 78.348 dB. The simulation results showed that the proposed method resulted in better denoising performance as compared to conventional filtering approaches.