Abstract
Content-addressable memory (CAM) performs a parallel search operation by comparing the search data with all content stored in memory during a single cycle, instead of finding the data using an address. Conventional CAM designs use a dynamic CMOS architecture for high matching speed and high density; however, such implementations require the use of system clocks, and thus, suffer from timing violations and design limitations, such as charge sharing. In this paper, we propose a static-based architecture for a low-power, high-speed binary CAM (BCAM) and ternary CAM (TCAM), using a nanoelectromechanical (NEM) memory switch for nonvolatile data storage. We designed the proposed CAM architectures on a 65 nm process node with a 1.2 V operating voltage. The results of the layout simulation show that the proposed design has up to 23% less propagation delay, three times less matching power, and 9.4 times less area than a conventional design.
Highlights
High-speed and large-capacity data processing has become important in the fields of big data and artificial intelligence, which are the core of the fourth industrial revolution
When search data are input, content-addressable memory (CAM), which this study focuses on, compares the search data against all data stored in the data array simultaneously in parallel
It is not possible to manufacture high-capacity memory with existing CMOS-based CAMs because they have a lower density than static random-access memory (SRAM)/dynamic random-access memory (DRAM)
Summary
High-speed and large-capacity data processing has become important in the fields of big data and artificial intelligence, which are the core of the fourth industrial revolution. As a specific memory location, called the address, must be assigned during this process, sequential memory operations are inevitable for random-access memory devices [1,2,3,4,5] For this reason, conventional random-access memory devices are not suitable for the high-speed and low-power large-capacity data processing required for big data and artificial intelligence. To read the bit stored in the SRAM, a high signal is applied to the WL CAMs have three modes: write, read, and search. They operate in the same manner as SRAMCsAiMn sthheawverittheraenedmroeaddesm: wodrietes., Freoarde,xaanmdpsleea, rtcohs.tTorheeya ‘o1p’einraateminemthoerysacmelel,ma a‘1n’ner as SRAMs in the write and read modes. If the SL precharge is used, the two NMOSs connected in series in the matcIhninagdcdiirtciuoint,airfetthuernSeLdporffecbheaforrgeeaismuastcehd,optheerattwioon NisMpeOrfSosrmcoendn. eHcteendcei,nthseerpiuesll-idnotwhen mpaatthchthinagt ccoirncnueitctasrtehteuMrnLedtooGffNbDefoisreblaocmkaetdchtooppreervaetinotnaids ipscehrfaorrgme.eIdn. aHdednictieo,nthteo tphuelsl-e dtaocwtincsp, asttuhdthieast hcoavnenebcetesnthceonMdLuctoteGdNonDvisarbilooucskemdettohopdresvteonrteadudcisechpaorwgee.rIcnoandsudmitipotniotno; tfhoerseextaamctpiclse,,satupdrieecshhaargvee-bfreeeenCcAonMduccirtceuditonthvaatreiloimusinmaetethsotdhes tporerecdhuarcgeepcoiwrceuritcotonrseudmupc-e tpioonw; efrorcoenxsaummpplet,ioanpwrehcehnaragem-firsemeaCtcAhMoccciurcrsui[t24th] aotrealiCmAinMatecsircthueitpurseicnhgaargneAcNircDuigtattoe rtehdaut cyeiepldosw‘e1r’ cwohnesnumalpl btiiotsnawrehe‘1n’ aanmdisymiealdtcsh‘0o’c, cifuersve[2n4o] noer abiCt AdoMescniroctumit autscihng[2a5n].AND gate that yields ‘1’ when all bits are ‘1’ and yields ‘0’, if even one bit does not match [25]
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