Testing Comparison and Delay Faults of TCAMs With Asymmetric Cells

Abstract

Ternary content addressable memory (TCAM) is one key component in high-performance networking applications. An asymmetric TCAM cell consists of a binary content addressable memory (BCAM) bit and a mask bit. In this paper, we analyze comparison faults of the asymmetric TCAM cell based on BCAM comparison faults. Also, two delay faults for covering delay defects in the comparison circuits of a TCAM are proposed. Then two march-like test algorithms T <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">H</sub> and T <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">PAE</sub> are proposed to cover the comparison faults and delay faults of the comparison circuits in TCAMs with asymmetric cells. The test algorithm T <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">H</sub> requires 7N Write operations and (3N + 2B) Compare operations to cover the comparison faults of an N × B-bit TCAM with Hit output only; and the test algorithm Tpae requires 4N Write operations and (3N + 2B) Compare operations to cover the comparison faults of an N × B-bit TCAM with priority address encoder (PAE) output.