Ternary Content Addressable Memory Research Articles

A Digital Processing in Memory Architecture Using TCAM for Rapid Learning and Inference Based on a Spike Location Dependent Plasticity

In this paper, we present a digital processing in memory (DPIM) configured as a stride edge-detection search frequency neural network (SE-SFNN) which is trained through spike location dependent plasticity (SLDP), a learning mechanism reminiscent of spike timing dependent plasticity (STDP). This mechanism allows for rapid online learning as well as a simple memory-based implementation. In particular, we employ a ternary data scheme to take advantage of ternary content addressable memory (TCAM). The scheme utilizes a ternary representation of the image pixels, and the TCAMs are used in a two-layer format to significantly reduce the computation time. The first layer applies several filtering kernels, followed by the second layer, which reorders the pattern dictionaries of TCAMs to place the most frequent patterns at the top of each supervised TCAM dictionary. Numerous TCAM blocks in both layers operate in a massively parallel fashion using digital ternary values. There are no complicated multiply operations performed, and learning is performed in a feedforward scheme. This allows rapid and robust learning as a trade-off with the parallel memory block size. Furthermore, we propose a method to reduce the TCAM memory size using a two-tiered minor to major promotion (M2MP) of frequently occurring patterns. This reduction scheme is performed concurrently during the learning operation without incurring a preconditioning overhead. We show that with minimal circuit overhead, the required memory size is reduced by 84.4%, and the total clock cycles required for learning also decrease by 97.31 % while the accuracy decreases only by 1.12%. We classified images with 94.58% accuracy on the MNIST dataset. Using a 100 MHz clock, our simulation results show that the MNIST training takes about 6.3 ms dissipating less than 4 mW of average power. In terms of inference speed, the trained hardware is capable of processing 5,882,352 images per second.

A Novel Cascadable TCAM Using RRAM and Current Race Scheme for High-Speed Energy-Efficient Applications

In this work, a novel ternary content addressable memory (TCAM) design is proposed using resistive random-access memory (RRAM) array in 2T2R configuration. The suggested memory array adopts the current-race (CR) sensing mechanism incorporated with a match-line (ML) booster in the sensing amplifier (SA) to improve energy efficiency, search speed and tolerance to RRAM switching variation. Several innovations are implemented to enhance the design further. For large TCAM arrays, match-line sensing amplifier (MLSA) direct cascading (DC) and an SR-latch cascading (SRC) schemes are proposed and compared in search speed, energy efficiency and MLSA noise margin. A same clock phase cascading (SCPC) scheme is also introduced to reduce latency in cascading structure by placing evaluation phase of all stages in the same clock phase. Furthermore, an RRAM-based tunable delay element (RRAM-TDE) is used in the TCAM design to provide flexibility and robustness against RRAM switching variation. The resulting system demonstrates excellent speed, energy and area efficiency against other TCAM designs using CMOS and emerging non-volatile memory (eNVM). To the best of our knowledge, the proposed 64-bit 1-stage TCAM system's speed and energy consumption match the best performance reported by other eNVM-based TCAM designs. The proposed design on a 128-bit 2-stage system also has speed and energy consumption comparable to SRAM-based TCAMs with the extra advantages of (a) compact size (90% reduction) and (b) non-volatility.

A Low-Energy DMTJ-Based Ternary Content- Addressable Memory With Reliable Sub-Nanosecond Search Operation

In this paper, we propose an energy-efficient, reliable, hybrid, 10-transistor/2-Double-Barrier-Magnetic-Tunnel-Junction (10T2DMTJ) non-volatile (NV) ternary content-addressable memory (TCAM) with sub-nanosecond search operation. Our cell design relies on low-energy-demanding MTJs organized in a low-complexity voltage-divider-based circuit along with a simple dynamic logic CMOS matching network, which improves the search reliability. The proposed NV-TCAM was designed in 28nm FDSOI process and evaluated under exhaustive Monte Carlo simulations. When compared to the best previous proposed NV-TCAMs, our solution achieves lower search error rate (3.8×) and lower write and search energy (–73% and –79%, respectively), while also exhibiting smaller area footprint (–74%). Such benefits are achieved at the expense of reduced search speed.

Ultradense One-Memristor Ternary-Content-Addressable Memory Based on Ferroelectric Diodes

In this Letter, for the first time, one-memristor (1M)-based ternary-content-addressable memory (TCAM) with an ultradense 4F2 cell area is proposed on a single reconfigurable TiN/hafnium zirconium oxide (HZO)/indium gallium zinc oxide (IGZO)/TiN ferroelectric (FE) diode. By modulating the FE-polarization-controlled Schottky junction that exists at the interface, reconfigured P–N, N–P, and ohmic like junctions of the FE diodes were designed for ‘0’, ‘1’, and ‘X’ storage states in the TCAM cell, respectively. In addition to non-volatile FE polarization for data storage, ambipolar-like behavior induced by the symmetrical junction characteristics was obtained on the diodes for searching queries. Using both non-volatile and ambipolar-like characteristics, typical TCAM functions with a maximum driving on/off ratio of ~500 were confirmed experimentally on a single FE diode, indicating the great potential of this memory device in area-efficient artificial intelligence processors.

Perfect Hash-Based Routing Lookup for LEO Constellation Backbone Network

The performance of packet forwarding mainly relies on the routing lookup (RL) in high-speed routers and switches. Due to the network topology change and the limited resource on aerospace devices, the RL strategy for LEO constellation backbone networks should be specifically designed. Targeting lower resource consumption, we first propose the perfect hash-based RL, including a Perfect Hash Function (PHF) for metarule space compression plus random access for the output interface. A Satellite Perfect Hash Function (SPHF) algorithm is proposed to generate efficient hash functions with limited storage. For 10000 randomized keys, the SPHF algorithm constructs 50-Kb PHFs in 3.05 milliseconds with 538 Kb storage. Then we design the Routing-oriented Hash Function (RHF) algorithm by fusing the perfect hash and RL, and optimize RHF towards the hardware implementation. The RHF algorithm is robust to different RL scenarios. In the FPGA (xc7k70t-fbv900-1) experiment with 10000 32-bit metarules and 4 output interfaces, a typical RHF algorithm (RHF1) costs only 13.2 ns and 1429 equivalent LUTs to lookup each packet under 312.5 MHz clock frequency. Compared with most advanced Ternary Content Addressable Memory (TCAM) based implementations, RHF1 reduces the storage and logic resources by at least an order of magnitude while keeping comparable lookup latency in the same FPGA Chip. This paper provides a design mentality for the RL of LEO constellation backbone networks.

LtRFT: Mitigate the Low-Rate Data Plane DDoS Attack With Learning-To-Rank Enabled Flow Tables

Software-Defined Networking (SDN) switches typically have limited ternary content addressable memory (TCAM) that caches the flow entries on the data plane. The scarcity and strong resource competitiveness of TCAM space put the flow tables at the risk of malicious Distributed Denial-of-Service (DDoS) attacks. In this paper, we propose LtRFT, a Learning-To-Rank (LtR) based scheme for mitigating the low-rate DDoS attacks targeted at flow tables. LtRFT consists of three modules: <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">monitor</i> , <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ranker</i> , and <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mitigator</i> . <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Monitor</i> manages the flow table status and sends alerts to other modules after detecting attacks. <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Ranker</i> models the attack mitigation problem as a flow entry ranking task, and ranks malicious flows with a high eviction priority using a pairwise-based LtR algorithm. The <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mitigator</i> frees up the flow table space by deleting malicious flow entries according to the flow entry ranking sequence generated by <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ranker</i> . We introduce LtR to network attack detection innovatively and use both classification and information retrieval metrics to describe and evaluate LtRFT. Extensive experiments were conducted to validate the effectiveness and robustness of LtRFT in detecting and mitigating the low-rate data plane DDoS attacks. LtRFT can detect malicious attack flows with an accuracy of over 96%, and can reduce the attack flow duration by 97.7% with an average extra latency of 0.5 seconds, which proves that LtRFT is practicable in SDN deployments.

Large Scale LEO Satellite Networks for the Future Internet: Challenges and Solutions to Addressing and Routing

This document analyses the problems and challenges of addressing and routing to Low Earth Orbit (LEO) satellites used for the future Internet. It focuses on the scenario where Inter-Satellite-Links (ISL) are used for massive LEO satellite constellation. Such LEO satellite network is the key to the Non-terrestrial Network (NTN) integration with 5G and beyond. The paper describes two categories of solutions. One is based on IPv6 and another is based on a new protocol, New IP. The two categories of solutions are a) using new types of addresses for LEO satellites and b) new concepts for routing with these addresses. The semantic addressing scheme leverages the characteristics of satellites with known orbit elements; and simplifies the satellite identification by using limited indexes. The routing method combines semantic addressing with source routing and generates a new semantic routing scheme. Compared with traditional methods, the new proposals dramatically reduce the workload in satellite, such as table size, Ternary Content-addressable memory (TCAM) lookups, and packet header size. Thus it is more suitable to networks in space where the harsh environment limits the hardware performance, power consumption, link bandwidth and system complexity.

Data and Computation Reuse in CNNs Using Memristor TCAMs

Exploiting computational and data reuse in CNNs is crucial for the successful design of resource-constrained platforms. In image recognition applications, high levels of input locality and redundancy present in CNNs have become the golden goose for skipping costly arithmetic operations. One promising technique for this consists in storing function responses of some input patterns into offline lookup tables and replacing online computation with search operations, which are highly efficient when implemented by emerging non-volatile memory technologies. In this work, we rethink both algorithm and architecture for exploiting locality and reuse opportunities by replacing entire convolutions with searches on Content-addressable Memories. By previously calculating convolution results and building compact lookup tables with our novel clustering algorithm, one can evaluate activations at constant time complexity, also requiring a single read operation of the current input tensor. Then, we devise a reconfigurable array of processing elements based on memristive Ternary Content-addressable Memories to efficiently implement the algorithmic solution and meet the flexibility requirements of several CNN architectures. Results show that our design reduces the number of multiplications and memory accesses proportionally to the number of convolutional layer channels. The average performance is 1,172 and 82 FPS for AlexNet and VGG-16 models, thus outperforming state-of-the-art works by 13×.

Ferroelectric Devices for Content-Addressable Memory.

In-memory computing is an attractive solution for reducing power consumption and memory access latency cost by performing certain computations directly in memory without reading operands and sending them to arithmetic logic units. Content-addressable memory (CAM) is an ideal way to smooth out the distinction between storage and processing, since each memory cell is a processing unit. CAM compares the search input with a table of stored data and returns the matched data address. The issues of constructing binary and ternary content-addressable memory (CAM and TCAM) based on ferroelectric devices are considered. A review of ferroelectric materials and devices is carried out, including on ferroelectric transistors (FeFET), ferroelectric tunnel diodes (FTJ), and ferroelectric memristors.

Memtransistor-Based Ternary Content-Addressable Memories: Design and Evaluation

The memtransistor (MT) based on 2-D materials is considered a promising candidate to extend Moore’s law, thanks to its scalability. As a hybrid integration of a memristor and a transistor, MT combines the electrical properties of memristor-based one-transistor one-resistor (1T-1R) structures (i.e., nonvolatile resistive switching and gate selection) into a single compact device. In this work, we evaluate MT technology from an application perspective and explore its use in ternary content-addressable memory (TCAM) systems. Based on characterization data from a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${10} \times {10}$ </tex-math></inline-formula> MoS2-based MT crossbar array, we propose two designs of MT-based TCAM (i.e., bitcells and TCAM array implementations and layouts). We also explore the design space of TCAM parameters and compare the performance and reliability of the proposed TCAM designs. In particular, we demonstrate that the use of MT technology facilitates the implementation of long TCAM words (>2 kbits) at low MT resistance ratios and search voltages, which is desirable for long TCAM endurance.

Computational Associative Memory with Amorphous Metal‐Oxide Channel 3D NAND‐Compatible Floating‐Gate Transistors (Adv. Electron. Mater. 12/2022)

Massively Scalable Ternary Content-Addressable Memories In article number 2200643, Xunzhao Yin, Xiao Gong, and co-workers present high-performance floating-gate transistors with an amorphous-InGaZnO channel and the application in ternary content addressable memories (TCAMs). The two-transistor configuration and the extremely low OFF current of the TCAM cell significantly improve the scalability of the TCAM array.

Static random‐access memory with embedded arithmetic logic units for in‐memory computing and ternary content addressable memory operation

Static random‐access memory with embedded arithmetic logic units for in‐memory computing and ternary content addressable memory operation

Energy Efficient and Low dynamic power Consumption TCAM on FPGA

Artificial Intelligence [AI] and networking applications extensively incorporate Field Programmable Gate Arrays [FPGA] - based Ternary Content Addressable Memories [TCAM]. Since FPGAs cannot support TCAMs, they must be emulated with SRAM-based memories, requiring FPGA resources. Compared to state-of-the-art designs, the proposed FPGA-based TCAM implementation will save significant resources. This methodology makes use of the Lookup Table RAMS (LUTRAMs), slice carry-chains, and flip-flops (FF) allowing simultaneous mapping of rules and deeper pipelining respectively. The TCAM implementation results in lower power consumption, lesser delays, and lower resource utilization. It outperformed conventional FPGA-based TCAMs in terms of energy efficiency (EE) and performance per area (PA) by at least 3.34 and 8.4 times respectively, and 56% better than existing FPGA designs. The proposed method outperforms all previous approaches due to its low dynamic power consumption when considering the huge size of TCAM emulation on SRAM-based FPGAs.

GeNVoM: Read Mapping Near Non-Volatile Memory.

DNA sequencing is the physical/biochemical process of identifying the location of the four bases (Adenine, Guanine, Cytosine, Thymine) in a DNA strand. As semiconductor technology revolutionized computing, modern DNA sequencing technology (termed Next Generation Sequencing, NGS) revolutionized genomic research. As a result, modern NGS platforms can sequence hundreds of millions of short DNA fragments in parallel. The sequenced DNA fragments, representing the output of NGS platforms, are termed reads. Besides genomic variations, NGS imperfections induce noise in reads. Mapping each read to (the most similar portion of) a reference genome of the same species, i.e., read mapping, is a common critical first step in a diverse set of emerging bioinformatics applications. Mapping represents a search-heavy memory-intensive similarity matching problem, therefore, can greatly benefit from near-memory processing. Intuition suggests using fast associative search enabled by Ternary Content Addressable Memory (TCAM) by construction. However, the excessive energy consumption and lack of support for similarity matching (under NGS and genomic variation induced noise) renders direct application of TCAM infeasible, irrespective of volatility, where only non-volatile TCAM can accommodate the large memory footprint in an area-efficient way. This paper introduces GeNVoM, a scalable, energy-efficient and high-throughput solution. Instead of optimizing an algorithm developed for general-purpose computers or GPUs, GeNVoM rethinks the algorithm and non-volatile TCAM-based accelerator design together from the ground up. Thereby GeNVoM can improve the throughput by up to 3.67×; the energy consumption, by up to 1.36×, when compared to an ASIC baseline, which represents one of the highest-throughput implementations known.

Re-FeMAT: A Reconfigurable Multifunctional FeFET-Based Memory Architecture

Most of current processing-in-memory (PIM) architectures are application specific, that is, they can only accelerate particular functions, e.g., matrix-vector dot product for neural network acceleration. However, practical applications usually involve various functions. In order to accelerate different functions, various accelerators, and dedicated circuits have been proposed. In this work, by exploring the similarities among some commonly used dedicated circuits, we adopt ferroelectric field-effect transistors (FeFETs) to build a reconfigurable multifunctional memory architecture named Re-FeMAT. Re-FeMAT is composed of multiple processing elements (PEs). Each PE is not only a nonvolatile memory array, but also can perform logic operations (i.e., the PIM mode), convolutions (i.e., the binary convolutional neural network and the convolutional neural network (CNN) acceleration mode) and content search (i.e., the ternary content-addressable memory (TCAM) mode) without changing the circuit structure. Re-FeMAT can support applications that require multiple functions. As an example, by configuring different PEs to different working modes and using a simulated annealing algorithm or a tabu search algorithm to optimize the task-PE assignment, Re-FeMAT can completely accelerate few-shot learning applications. Our simulation results based on a calibrated FeFET model show that the proposed Re-FeMAT architecture achieves better performance and power efficiency than the previous FeMAT architecture. Compared with FeFET-based single-functional circuits, though the power dissipation of Re-FeMAT is higher in some modes, the power-delay product is still smaller. Compared with a state-of-the-art FeFET-based multifunctional accelerator named attention-in-memory, Re-FeMAT achieves lower power, latency, and energy when accelerating a complete few-shot learning task.

Beol-Compatible Ingazno-Based Devices for 3D Integrated Circuits

Due to its attractive materials and electrical properties, indium-gallium-zinc-oxide (IGZO) has been extensively researched in many emerging technologies, especially for three-dimensional (3D) monolithic integration and back-end-of-line (BEOL) compatible applications [1]. On the pathway toward the realization of high-performance 3D monolithic integrated chips (ICs), a wide range of building blocks with different functionalities are required. 3D monolithic ICs also demand optimization in device performance and circuit architecture design.In this paper, we discuss our recent research development in IGZO-based techniques at both device and circuit levels. This includes nanowire structure for IGZO-based transistors, as well as the BEOL-compatible ferroelectric ternary content-addressable memory (TCAM) and embedded dynamic random-access-memory (eDRAM) for compute-in-memory (CiM) using IGZO-based transistors.A novel digital etch technique for amorphous IGZO (α-IGZO) material as well as the formation of α-IGZO nanowires were realized, enabling high performance α-IGZO nanowire field-effect transistors (NWFETs) with ultra-scaled nanowire width (W NW) [2]. The scanning electron microscopy (SEM) images of α-IGZO nanowire before and after the digital etch show that the nanowire structure as well as W NW reduction after digital etch can be clearly observed. The smallest α-IGZO nanowire after digital etch has a W NW of ~20 nm. By leveraging the ultra-scaled nanowire structure, the NWFET with the smallest W NW achieves decent subthreshold swing of 80 mV/decade as well as high peak extrinsic transconductance (G m,ext) of 612 μS/μm at a drain to source voltage (V DS) = 2 V (456 μS/μm at V DS = 1 V). As compared with previous works in literature, our IGZO NWFET achieves one of the highest peak G m among all IGZO-based FETs. α-IGZO ferroelectric FETs (Fe-FETs) with a metal-ferroelectric-metal-oxide-semiconductor (MFMIS) structure were further realized based on the α-IGZO transistor process modules. The smallest L CH is as small as 40 nm. The cross-sectional transmission electron microscopy (TEM) image of the device shows sharp interface. The α-IGZO Fe-FETs achieve a large memory window of 2.9 V, high endurance of 108 cycles, high conductance ratio, and small cycle-to-cycle variation. By leveraging the low temperature processed α-IGZO Fe-FETs with good electrical characteristics, a BEOL-compatible ferroelectric TCAM circuit with 2 Fe-FETs connected in parallel was realized [3], showing an extremely large sensing margin. In addition, such α-IGZO Fe-FET TCAM reduces the transistor number from 16 to 2 as compared to traditional SRAM-based TCAM. Smaller cell size and higher energy efficiency can also be obtained.IGZO transistors can play an important role in in-memory computing as well. SEM image of the eDRAM CiM cell shows utilization of IGZO transistors. The smallest device has L CH of 45 nm [4]. The IGZO transistor-based eDRAM CiM with differential cell structure achieves low leakage current, low variation, low charge loss sensitivity, and the control-friendly charge-domain computing without DC power. By evaluating the key figure-of-merits, including precision, power efficiency, computing density, retention time, and robustness, it can be concluded that our IGZO transistor-based eDRAM CiM is promising for low-power and scalable compute-in-eDRAM design. Acknowledgments: This work is supported by Singapore Ministry of Education (Tier 2: MOE2018-T2-2-154, Tier 1: R-263-000-D65-114).

FeFET Multi-Bit Content-Addressable Memories for In-Memory Nearest Neighbor Search

Nearest neighbor (NN) search computations are at the core of many applications such as few-shot learning, classification, and hyperdimensional computing. As such, efficient hardware support for NN search is highly desired. In-memory computing using emerging devices offers attractive solutions for NN search. Solutions based on ternary content-addressable memories (TCAMs) offer high energy and latency improvements for NN search at the expense of accuracy. In this work, we propose a novel distance function that can be natively evaluated with multi-bit content-addressable memories (MCAMs) based on ferroelectric FETs (FeFETs) to perform a single-step, in-memory NN search. We evaluate the efficacy of FeFET MCAMs in the context of few-shot learning applications with different datasets. As an example, we achieve a 78.54% accuracy for a 5-way, 5-shot classification task for the mini-ImageNet dataset (only 1.5% lower than software-based implementations) when using a 3-bit MCAM for NN search. We consider the effects of FeFET threshold voltage variations on the application accuracy and analyze the area and search energy requirements of FeFET MCAMs for accurate operations. Our results indicate that MCAMs require 2× lower area and search energy than TCAMs to achieve the same accuracy. Furthermore, we experimentally demonstrate a 2-bit implementation of FeFET MCAM using AND arrays from GLOBALFOUNDRIES to further validate the design concept.

Computational Associative Memory with Amorphous Metal‐Oxide Channel 3D NAND‐Compatible Floating‐Gate Transistors

Abstract3D NAND has been enabling continuous NAND density and cost scaling beyond conventional 2D NAND since sub‐20‐nm nodes. However, its poly‐Si channel suffers from low mobility, instability caused by grain boundaries, and large device‐to‐device variations in electrical characteristics at highly scaled device dimensions. These drawbacks can be overcome by introducing an amorphous indium‐gallium‐zinc‐oxide (a‐IGZO) channel, which has the advantages of ultralow OFF current, back‐end‐of‐line compatibility, higher mobility than poly‐Si, and free of grain boundaries due to the amorphous nature. In this work, ultrascaled floating‐gate (FG) transistors with a channel length down to 60 nm are reported, achieving the highest ON current of 127 µA µm−1 among all reported a‐IGZO‐based flash devices for high‐density, low‐power, and high‐performance 3D NAND applications. Furthermore, a nonvolatile and area‐efficient ternary content‐addressable memory (TCAM) with only two parallel‐connected a‐IGZO FG transistors is experimentally demonstrated to address the TCAM scalability issue. Experimentally calibrated array‐level simulations show that this design achieves at least a 240 × array‐size scalability and a 2.7‐fold reduction in search energy than TCAMs based on complementary metal‐oxide‐semiconductor technology using 16 transistors, two‐transistor‐two‐resistive random access memory, and two‐ferroelectric field‐effect‐transistor.

Evaluation of Hash Join Operations Performance Executing on SDN Switches: A Cost Model Approach

Distributed database systems store and manipulate data on multiple machines. In these systems, the processing cost of query operations is mainly impacted by the data access latency between machines over the network. With recent technology advances in programmable network devices, the network switches provide new opportunities for dynamically managing the network topology, enabling the data processing on these devices with the same network throughput. In this paper, we explore the programmable network switches in query processing, evaluating the processing performance of a cost model in executing the hash join operation. We assume the storage of the hash table built from outer relation and the materialization of the join probing are made in switches using advanced matching techniques similar to package inspections enabled by Ternary Content-Addressable Memories (TCAM) or SRAM via hashing. Our results show that processing the hash join operation using network switches achieved the best results compared to traditional servers, with an average time reduction of 91.82% (Query-10 from TPC-H) and 96.52% (Query-11 from TPC-H).

A&amp;B: AI and Block-Based TCAM Entries Replacement Scheme for Routers

With the ever-increasing deployment of 5G and IoT, the number of end-hosts/terminals is increasing rapidly, so that routers have to cache more and more forwarding entries to guarantee communication reachability of these terminals, which makes Ternary Content Addressable Memory (TCAM)-based routers keep expanding resource requirements. However, the design and implementation of large-capacity TCAM-based routers are faced with such challenges: difficult circuit design, high production cost and energy consumption, thereby posing an urgent requirement on a lightweight TCAM that can still maintain those massive communication connections. In this paper, we aim to design a lightweight router with small storage requirement while still retaining the original communication connection performance, which is not straightforward due to the following two challenges: First, under the condition of massive sequential flow data, it’s difficult to accurately and timely select the entries to cache for a small capacity TCAM. Second, given the strict prefix matching principle, how to efficiently insert the selected entries into TCAM is also challenging. To address these problems, we propose A&B: an AI-based Routing entry prediction strategy (AIR) and a Block-based entry Insertion Tactic (BIT). AIR can precisely select entries by conducting accurate entry predictions, which converts dynamic flow-based prediction into stable and parallelizable entry-based prediction by decoupling spatio-temporal characteristics. BIT optimizes entry insertion by isolating TCAM into several blocks, thus eliminating the time-consuming entry movements. The experiment results based on real backbone traffic show that our lightweight A&B achieves comparable performance compared to the traditional schemes by using only 1/8 TCAM storage.