Superconducting Logic Research Articles

Superconducting digital electronics

Single-flux quantum logic (SFQ) circuits, in which a flux quantum is used as an information carrier, have the possibility for opening the door to a new digital system operated at over 100-GHz clock frequency at extremely low power dissipation. The SFQ logic system is a so-called pulse logic, which is completely different from the level logic for semiconductors like CMOS, so circuit design technologies for SFQ logic circuits have to be newly developed. Recently, much progress in basic technologies for designing SFQ circuits and operating circuits at high speeds has been made. With advances in these design tools, large-scale circuits including more than several thousand junctions can be easily operated with the clock frequency of more than several tens of gigahertz. High-end routers and high-end computers are possible applications of SFQ logic circuits because of their high throughput nature and the low power dissipation of SFQ logic. In this paper, recent advances of SFQ circuit design technologies and recent developments of switches for high-end routers and microprocessors for high-end computers that are considered possible applications for SFQ logic will be described.

Rapid single-flux quantum logic using π-shifters

We have found that the size of some rapid single-flux quantum (RSFQ) logic cells based on conventional 0-type Josephson junctions can be significantly reduced by using a π-type junction as a phase shifter in passive (nonswitching) mode. In comparison with the recently suggested active (switching) π-junctions mode, the passive mode offers much greater operation margins for their critical current Icπ. This gives π-junctions a chance to be implemented in RSFQ designs in the near future. As an example, we have simulated the operation of a toggle flip flop with zero-geometrical inductance of the fluxon storage loop. Simulations show that the parametric inductance of the π-junction and its normal resistance Rn form a low-pass filter, which sets the low limit for π-junctions IcπRn product, but offers a wide range of variations of the other parameters. The possible reduction of RSFQ cell size by using π-junctions opens the way to scale superconducting logic circuits down to the submicron dimensions.

Cell based design methodology for BDD SFQ logic circuits: A high speed test and feasibility for large scale circuit applications

We have proposed a cell-based design methodology for SFQ logic circuits based on a binary decision diagram (BDD) and implemented a BDD SFQ standard cell library using a Hypres Nb process. In this design methodology, any logic function can be implemented by connecting binary switches. Since the circuits are dual rail logic and do not need a global clock, difficulty in the timing design is reduced considerably. In our cell-based design approach, the cell library is composed of only five kinds of basic cells, whose circuit parameters are optimized so as to remove the inter-cell interaction. At the layout level, the cells have the identical size so that circuits can be implemented by simply embedding the basic cells. In this study we have performed an on-chip high-speed test of the BDD SFQ logic circuits. The test system consists of two four-bit data-driven self-timed (DDST) shift registers with a ladder type clock generator. We have confirmed 12 GHz operations of the BDD SFQ logic circuit. We have also examined circuit size dependence of the DC bias margin of large BDD SFQ circuits.

Pipelined architecture based on single flux quantum with resettable latch

We have already proposed single flux quantum with resettable latch (SFQ-RL). SFQ-RL was proposed as a new SFQ logic, which consists of “L-gate”, “confluence buffer” and “splitter”. We can realize the pipelined circuits easily using SFQ-RL, because the pipelined circuits are constructed by connecting L-gates in series. We have reported the full operation of the half adder based on SFQ-RL before. As the application of SFQ-RL to the more complicated circuits with a pipelined structure, we have designed pipelined carry save serial adder (CSSA). We have confirmed the partial operation of CSSA.

A new concept for ultra-low power and ultra-high clock rate circuits

Compared with semiconductors, SFQ logic is very fast and dissipates extremely low power. But it does not approach the theoretical power dissipation associated with an SFQ switching event and single gate speed in complex circuits. For large circuits and systems, e.g., petaflops computing, we must reduce on-chip dissipation, achieve faster clocked logic operation, and increase gate density. CMOS logic dissipates the energy required to switch a transistor pair and dissipates no power between switching events. We describe a new SFQ circuit concept that mimics CMOS to achieve ultra-low power dissipation and ultra-high clock rates. This results in physically compact, self-clocked, complementary logic (SCCL), in which clock distribution is frequency-independent. The basic element in this logic family is a simple two-junction comparator. Using TRW's 2 kA/cm/sup 2/ Nb design rules, we simulated basic digital components: shift register, AND, OR, and NOT at 20 GHz. We present the simulated and measured performance.

Superconducting digital electronics

Superconducting devices have intrinsically superior characteristics to those of semiconductor devices. Presently, we can fabricate more than twenty thousand junctions on one chip using niobium technology. We have demonstrated the operation of a network system with a superconducting interconnection chip using voltage-state logic. Single flux quantum devices are promising for future superconducting applications because the clock frequency of SFQ logic is higher than that of voltage-state. We have proposed a high-end switch based on hybrid architecture using optical devices, semiconductors and SFQ devices. To demonstrate the high-speed operation of SFQ circuits, we developed an arbiter circuit that uses SFQ components and the arbiter circuit operates at 60 GHz. We also have developed a high Tc superconducting (HTS) SFQ sampler system for observing ultra-fast signal waveforms. In addition, we will discuss the prospects of future superconducting devices based on the fabrication technologies we developed.

Bit error probabilities in high temperature superconductor logic

We present error rate simulations for a single flux quantum logic circuit which include statistical variations in the circuit parameters. We find that the fabrication yield, junction critical margins, and bit error probabilities of the nominal circuit can give a false impression of the performance of practical circuits. For our study circuit, the toggle flipflop, we find that, although the standard figures of merit may vary only marginally with design rules, the average error rate can differ by a factor of 104. Furthermore, for a state-of-the-art technology, the error rates of different realizations of the same design actually span 10 orders of magnitude. These results highlight the inadequacy of current figures of merit to gauge the performance of high temperature superconductor designs.

Experimental demonstration of single flux quantum logic with resettable latch

We report experimental demonstrations of logic functions based on single flux quantum logic with resettable latch (SFQ-RL) logic. SFQ-RL has been proposed as new SFQ logic, which enables us to initialize the whole circuit. This initialization function is essential for the state machine into which conventional SFQ logic is classified, and makes SFQ logic more applicable to a large-scale logic system, such as a processor. In addition, the function can prevent circuits from performing the failed operation caused by a trapped flux in storage loops. The logic consists of three primitives, which can compose any logic function. We have experimentally demonstrated the operation of half adder based on SFQ-RL with the bias margin of /spl plusmn/16%. In order to examine the function of initialization, we designed and evaluated a pseudo random sequence generator by numerical simulation. In addition, we experimentally confirmed the initialization of the generator and circular buffer with the bias margin of /spl plusmn/20%.

Design and experimentation of BSFQ logic devices

Rapid single flux quantum (RSFQ) logic needs synchronous pulses for each gate, so the clock-wiring problem is more serious when designing larger scale circuits with this logic. So we have proposed a new SFQ logic which follows Boolean algebra perfectly by using set and reset pulses. With this logic, the level information of current input is transmitted with these pulses generated by level-to-pulse converters, and each gate calculates logic using its phase level made by these pulses. Therefore, our logic needs no clock in each gate. We called this logic `Boolean SFQ (BSFQ) logic'. In this paper, we report design and experimentation for an AND gate with inverting input based on BSFQ logic. The experimental results for OR and XOR gates are also reported.

HTS SFQ logic circuit built with YBCO grain boundary junctions

We have designed, fabricated, and operated an SFQ RS flip–flop based on YBCO grain boundary junctions formed on a SrTiO 3 bi-crystal substrate. The circuit consisted of a read SQUID and an RS flip–flop, which were magnetically coupled together. The circuit operated correctly in the temperature range of 65–71 K. Especially, at 71 K, this circuit operated correctly over the 100 reset–set operations without making errors. We also measured the effect of noise on switching a Josephson junction to the voltage state in an SFQ circuit.

Logic gates using stacked Josephson junctions

We investigate the possibility of making ultrafast superconducting logic gates using vertically stacked Josephson junctions. Employing flux quanta as information bits, we implement the functions of the logic gates AND, OR and EX-OR. Other logic functions and memory elements can be made by properly configuring these elementary logic gates. Design of these devices exhibits wide tolerance and flexibility in selecting the geometrical and electrical parameters.

Effect of thermal noise on the bit error rate of SFQ devices

To measure the effect of thermal noise on switching a Josephson junction to the voltage state a simple SFQ circuit constructed with resistively shunted Nb/AlO/sub x//Nb junctions was used. Based on a good agreement between the measured data and the thermal activation theory, the effect of thermal noise on the bit error rate of SFQ devices was studied, The effective thermal noise temperature of 10 K used to fit the data was higher than the bath temperature of 4.2 K. Careful circuit design to get large critical margins is necessary to achieve high operating temperature of SFQ logic devices.

C-axis microbridges for rapid single flux quantum logic

The c-axis microbridge (CAM) junction technology has an inherently low inductance due to its groundplaned geometry which should be well suited to SFQ logic applications. However, the critical currents of the conventional (2 /spl mu/m diameter) CAM technology are too high. Experiments with optical lithography have shown that junctions of /spl sim/0.5 micron dimension are required. A new process using electron beam lithography has been developed. The junction statistics even at this early stage of development look promising. To confirm the validity of the rest of the design and fabrication technology a CAM based RS Flip-Flop has been fabricated which shows the correct traversal of the state graph at 45 K.

SFQ data processing with set/reset information

We propose a new class of SFQ logic circuits. In this new approach, an SFQ pulse represents the transition between zero and one. By using these two bits of information, a one-to-one correspondence between input and output can be realized. Since the correspondence is then the same as in semiconductor circuits, this method permits logic design without clock elements. In order to carry out this logic, we propose the most fundamental element, a new DC/SFQ converter. A computer simulation and low-speed test were performed. Both results showed that this converter operates correctly with a wide margin. Moreover, this converter also provides the basis for many other logic elements such as AND, OR, and XOR.

Clock-driven on-chip testing for superconductor logic circuits

We have developed and demonstrated a clock-driven on-chip testing (CDOT) method for high-speed testing of superconductor logic circuits. This testing method uses an on-chip signal-pattern generator (SPG) driven by a clock signal. The SPG is based on a feedback shift register, in which a complement output of the last-stage D-flip-flop is fed back to the first-stage D-flip-flop. Thus, SPG generates a periodic signal-pattern when a clock signal is applied to it. The advantages of this testing method are that: (a) no external control signal is needed; (b) a simple SPG that consists of only D-flip-flops is used; (c) it is easy to extend to multi-bit testing. This greatly simplifies high-speed testing and design of test circuits. We have applied this method to the high-speed testing of the ring interface (RIF) circuit, which is an elemental circuit in our superconducting ring-network system. We have designed a test circuit, consisting of the RIF circuit and a 12-bit on-chip test-pattern generator, with resistor-coupled Josephson logic (RCJL). The test circuit includes about 1,400 Josephson-junctions. It has been fabricated using Nb/AlO/sub x//Nb Josephson-junction technology. As the result of the high-speed testing, full operation of the RIF circuit at 1-GHz clock frequency and proper operation of a sending part of the RIF circuit at 2-GHz clock frequency have been successfully verified.

Complementary Josephson junction devices and circuits: a possible new approach to superconducting electronics

We present a superconducting logic family whose operation relies on the availability of a current gain greater than one, based on the analogy to semiconductor complementary metal-oxide-semiconductor (CMOS) logic family. The Complementary Josephson Junction (CJJ) logic family utilizes two types of nonlatching devices: a conventional device and a complementary device. The conventional device has a finite critical current, and the complementary device has zero critical current with no input applied. When the input is high, the complementary device has a finite critical current, while the conventional device has zero critical current. The bias current can be steered between a branch with a complementary device and a branch with a conventional device performing logic (and memory) functions. We can also use a resistor as a load to a complementary device. We call this circuit topology the Resistor Complementary Josephson Junction (RCJJ) family. It is analogous to the semiconductor PMOS/resistor logic family. In this paper, we investigate methods of realizing complementary devices, and we present a preliminary analysis of speed, margins, and power dissipation in simple CJJ and RCJJ inverter circuits.

Development of radiation-hard particle detectors using Josephson tunnel junctions

Josephson tunnel junctions, due to their ultra-fast switching between different voltage states, are in principle capable of very fast position detection. This feature, together with the high radiation hardness of the constituting materials and the possibility of direct interfacing to ultra-fast superconductive logic families, makes Josephson tunnel junctions interesting candidates for new ultra-fast pixel detectors to be used at future colliders. Possible explanation of the detection mechanism in terms of an energy balance model is proposed, together with the identification of crucial parameters for detection sensitivity. A new approach for realising a detector integrated with read-out electronics is presented. Radiation hardness for both detector and electronics is discussed. High sensitivity to magnetic field is also addressed.

Operation of an HTS SFQ logic circuit

A Josephson junction biased below its critical current can switch to the voltage state by a thermal fluctuation. Thermal noise, rather than the critical temperature of high Tc materials, may limit the maximum operating temperature of superconductive digital circuits. Due to the technical difficulty of making the Tc digital circuits, the maximum operating temperature of these devices could only be estimated. Measurement of the effect of noise on switching a Josephson junction to the voltage state was made on a simple SFQ device constructed with resistively shunted Nb/AIOX/Nb. Good agreement was obtained between the measured data and the calculations based on thermal activation theory. Thermal activation theory could also explain the data obtained on a simple HTS SFQ device fabricated with YBCO grain boundary junctions formed on a STO bicrystal substrate. Large margins in SFQ circuits indicate the possible operation of high Tc SFQ circuits at high temperature.

Operation of high- Tc SFQ devices at near liquid nitrogen temperature

As the operating temperature of the SFQ logic circuits gets higher by using high- T c superconductors, the effect of noise on switching a Josephson junction to the voltage state becomes more important. In this paper, we report our work on high- T c SFQ RS flip-flop which was made with YBCO thin film deposited on a SrTiO 3 bi-crystal. The circuit operated correctly at 71 K over the 200 computer-generated clock cycles without making errors, where a reset or a set operation was made over one clock cycle. Good agreement between the measured data and the calculation based on the thermal activation theory was obtained. The effective noise temperature used to fit the data was much higher than the physical temperature. This could be due to the instrument noise. Improvement in the measurement set-up might reduce the effective noise temperature. Also our measurement results indicate that the elevation of the operating temperature near the liquid nitrogen temperature may not affect the margin of the circuit.

Stochastic simulation of SFQ logic

The high speed and low power of Single Flux Quantum logic (SFQ) are extremely attractive, and significant capabilities have been demonstrated in Nb technology. However the burden of cooling to 4.2K has been a barrier to its widespread implementation. The advent of High Temperature Superconductors (HTS), raises the prospect of more accessible temperatures. This paper examines some theoretical constraints on the implementation of SFQ in HTS, and derives some ideas about the parameters required of any HTS SFQ technology.