Subthreshold Leakage Current Research Articles

Modeling and Simulation Characteristics of a Highly-Sensitive Stack-Engineered Junctionless Accumulation Nanowire FET for PH3 Gas Detector

In this manuscript, a Stack Engineered Junctionless Accumulation Nanowire FET (SE-JAM-NW FET) has been proposed for low - power and high sensitivity phosphine (PH3) gas detection applications. In comparison to a standard nanowire FET, the SE-JAM-NW FET is used at nanoscale dimensions because of its inherent benefits, including low cost, improved portability, low Off- state current and increased On-state current with low - power consumption. To implement the SE-JAM-NW FET as a phosphine gas sensor, four catalytic metals, Platinum (Pt), Rhodium (Rh), Iridium (Ir) & Palladium (Pd) have been employed as gate electrodes. For designing gas sensor, various electric parameters like potential, electron concentration, recombination rate and electron velocity are evaluated for PH3 gas detection. To forecast the sensor’s response, analog characteristics like changes in drain current, transconductance & output conductance are being simulated for different catalytic metal work functions (200 meV, 150 meV, 100 meV and 50 meV) at the gate electrode. The variation in On-state current-to-Off-state current ratio (IOn/IOff), On-state current (IOn) & subthreshold leakage current (IOff) for sensing the gas molecules has been used to quantify the sensitivity. The effects of silicon pillar-based radius variation and channel length variation on the sensitivity-based parameters are also investigated. Each catalytic metal exhibits improved sensitivity with increased channel length and decreased radius. The outcomes of the ATLAS 3-D device simulator’s numerical simulation closely match with those of the derived analytical model.

Source of IC power consumption and low power design

In these years, with the continuous development of 14nm and 7nm chip processes and the increasing popularity of computers, cell phones, and smart homes, the growing market of electronic products and ultra-fine research for the reliability of the chip requirements gradually increased. The method of reducing power consumption in the new context of new technology is called the chip field die-cut concern. This paper mainly summarizes two aspects of power consumption sources and methods to reduce power consumption, to provide a reference basis for future research directions: First, the major sources of power consumption are static power consumption and dynamic power consumption. The primary sources of static power consumption are sub-threshold leakage and gate leakage current. This paper also mentions some other leakage currents, such as reverse bias PN junction current and induced leakage current, which can be more carefully considered when exploring methods to reduce power consumption. A more comprehensive consideration when exploring ways to reduce power consumption. Dynamic power consumption is mainly divided into Switching power and Internal power and short-circuit power. Then we summarize the existing methods which can reduce power consumption: Clock gating (including Clock gating without a latch and Clock gating with a latch), Dynamic voltage and frequency scaling, multi-supply and multi-voltage technology, Power gating and multi-threshold voltage. These methods are from a proprietary perspective to reduce power consumption.

Numerical Simulation of Hetero Dielectric Trench Gate JAM Gate-All-Around FET (HDTG-JAM-GAAFET) for Label Free Biosensing Applications

The label free detection of various biomolecules associated with different diseases has been proposed in this manuscript using a novel biosensor design named as the Hetero Dielectric Trench Gate Junctionless Accumulation Mode Gate-All-Around FET (HDTG-JAM-GAAFET). This biosensor employs a silicon cylindrical Gate All Around FET which operates in Junctionless Accumulation Mode (JAM) and has a hetero dielectric layer comprised of SiO2 and HfO2. The cylindrical gate structure’s metal gate is trenched into the Hafnium oxide dielectric layer, which provides the gate with enhanced control over the surface characteristics of the channel. A Trench Gate architecture in a hetero dielectric Gate All Around FET is emulated for the biosensing for the first time. The HDTG-JAM-GAAFET has been compared to Normal Gate JAM Gate-All-Around FET (NG-JAM-GAAFET) biosensors immobilizing a variety of neutral biomolecules and biomolecules having a range of positive and negative charges. The effect of biomolecules on HDTG-JAM-GAAFET biosensor’s output properties, including surface potential, electron concentration, threshold voltage drift (ΔVTH), subthreshold leakage current (IOFF), subthreshold slope (SS), switching ratio (ION/IOFF), ION current sensitivity, transconductance (gm), output conductance (gd), channel resistance (Rch) and intrinsic gain ( AVint ) has been studied. For instance, HDTG-JAM-GAAFET biosensor has drain ON-current sensitivity (SION) which is 67.68% greater for gelatin biomolecules, 69.4% higher for positive biomolecules, and 8% higher for negative biomolecules bound in the nanogap cavity than that of a Normal Gate JAM Gate-All-Around FET. The proposed device exhibits exceptional performance characteristics and it can effectively identify specific biomolecules to diagnose many diseases, such as breast cancer, lung cancer, and numerous viral infections, using their respective biomarkers.

Low-Leakage Double-Body MOSFET: A Promising Circuit-Level Technique for Deep-Submicron Analog Integrated Circuit Design

Since the leakage currents are dramatically increasing while the MOS transistors scale down to deep-submicron processes, the [Formula: see text]–[Formula: see text] characteristic of the channel is varied unintentionally. As a result, the analog integrated circuit (IC) designs based on it (at above 100-nm technologies) will malfunction. In this paper, a novel low-leakage double-body MOSFET (LLDB-M), as a circuit-level scheme in answering to the need for the current-mode analog IC design in deep-submicron processes, is proposed. In this technique, the sub-threshold and gate-oxide tunneling leakage currents (as two major parts) are reduced via lowering the gate-source voltage and increasing the threshold voltage of the MOS transistor. An LLDB-M consists of two typical transistors — the first one is the main transistor and the latter implements the shift-voltage to reduce the gate-source voltage and floor of the channel leakage currents. The drain, gate, and body of the main transistor as well as the body and source of the second one, organize the terminals of an LLDB-M. The proposed LLDB-M transistors are replaced with large-leakage transistors in a translinear loop in the weak inversion region and then the commonly-used circuits such-as the current mirror, one-quadrant multiplier-divider (at both up-down and stack topologies), the true RMS-DC converter, and the log-domain low-pass-filter are designed. The effectiveness and performance of the proposed LLDB-M technique and circuits are evaluated using HSPICE software in 22-nm BSIM4 CMOS process and Cadence Virtuoso tool in 65-nm TSMC CMOS technology. Post-layout simulation results show that the proposed circuit-level method by considerably reducing leakage currents could ensure the effective function of the current-mode analog IC designs in deep-submicron technologies. Also, comprehensive simulations have been performed to prove the robustness and reliability of the proposed circuits against process, voltage and temperature (PVT) changes.

Low-temperature deuterium annealing for improved electrical characteristics of SONOS

Deuterium annealing is a promising process technology for CMOS fabrication. Deuterium annealing effectively passivates interface traps at the Si-SiO2 interface, allowing for improvements in the electrical characteristics and reliability of CMOS. However, conventional deuterium annealing is typically performed at high temperatures above 400 °C, which can lead to unwanted dopant deactivation, random dopant fluctuation (RDF), and thermal-induced stress in the backend-of-the-line (BEOL). In this study, we demonstrate the use of deuterium annealing at low temperatures, resulting in improvements in SONOS devices. Device characterizations based on subthreshold swing (SS), on-state current (ION), off-state current (IOFF), and gate leakage current (IG), as well as time-of-flight secondary ion mass spectrometry (ToF-SIMS) are included to clarify the effects of annealing.

Studying the Performance of Underlap GAA-FET

Abstract: This paper investigates the performance of underlap Gate-All-Around Field Effect Transistor (GAA FET) of 22nm gate length and evaluates the short channel performance of the device. Underlap GAA FET structure can be utilized to increase the drive current of the nanowire devices. In this work, underlap rectangular GAA FET is designed by extension of underlap regions on source/drain of GAA FET to increase the performance. This underlap device is increasing the capacitances by adding the fringing capacitances to parasitic capacitances which increases the fringing field from gate electrode to underlap regions. In this also investigating the electrical parameters on various performance metrics like threshold voltage (Vth), ON current (ION), OFF current or subthreshold leakage current (IOFF), ON-OFF current ratio (ION/IOFF) and short channel effects such as Subthreshold slope (SS) and DIBL (Drain Induced Barrier Lowering) of underlap GAA FET are systematically evaluated and analysed. In the present study, GAA FET and underlap GAA FET device performances are investigated through ATLAS device simulator from Silvaco.

CNTFET-based Data Independent Power Efficient and Robust 8T SRAM Cell

A new carbon nano-tube field-effect transistors (CNTFETs) based Power Efficient and Robust 8T (PER-8T) SRAM cell is proposed to reduce sub-threshold leakage currents, data dependency by improving RBL swing due to which RSNM is improved. Leakage power is reduced by using only single pull-up transistor with High V t in storage latch. Half-select issue is eliminated since proposed work uses de-coupled read port. This CNTFET based proposed PER-8T cell is analysed for performance parameters like power, delay and stability and compared to 8T SRAM cells at 45 nm technology. All simulations are performed at supply voltage of 0.9 V considering Stanford Virtual Source CNTFET(VS-CNTFET) model. It shows that RSNM and WSNM are improved by 12.07%, 14.85%, 56% and 46.46%, 20.39%, 66.05% compared to single ended 8T SRAM cells available in recent literature. Effects of VS-CNTFET parameters such as dielectric material, temperature, oxide thickness and carbon nano tube diameter values on hold power is analysed and best values are considered. The cadence tool is used for measuring all design metrics at room temperature of 25 °C.

Radiation hard true single-phase-clock logic for high-speed circuits in 28 nm CMOS

True Single-Phase-Clock (TSPC) dynamic logic is widely used in high-speed circuits such as high-speed SERDES (Serializer/Deserializer) and frequency dividers. TSPC flip-flops (FF) are known for their high operational speed and low power consumption, compared to static FFs. Due to the relatively high leakage currents in modern CMOS processes, the use of leakage protection techniques of the storage nodes in TSPC must be considered, especially at high radiation doses. In this paper, the limitations originating from Total Ionization Dose (TID)-induced subthreshold leakage currents are analysed and radiation-hardening-by-design (RHBD) circuit techniques are proposed. Additionally, Single Event Upsets (SEU) are investigated by quantifying the critical charge of the leakage protected TSPC FF. The results are compared to both the static and the TSPC FF without leakage mitigation.

Influence of Bulk Doping and Halos on the TID Response of I/O and Core 150 nm nMOSFETs

The total ionizing dose sensitivity of planar 150 nm CMOS technology is evaluated by measuring the DC responses of nMOSFETs at several irradiation steps up to 125 krad(SiO2). Different TID sensitivities are measured for transistors built with different channel dimensions and operating voltages (I/O and core). The experimental results evidence strong relations between TID sensitivity and the doping profiles in the channel. I/O transistors have the highest TID sensitivity due to their thicker gate oxide and lower bulk doping compared with core devices. In general, narrow-channel devices have the worst degradation with negative threshold voltage shifts, transconductance variations and increased subthreshold leakage currents, suggesting charge trapping in shallow trench isolation (STI). The enhanced TID tolerance of short-channel core devices is most likely related to the increased channel doping induced by the overlapping of halo implantations. Finally, transistors fabricated for low-leakage applications exhibit near insensitivity to TID due to higher bulk doping used during the fabrication to minimize the drain-to-source leakage current.

Design and Development of Biosensors Based on Nano Tube Tunnel Field Effect Transistor

Tunnel Field Effect Transistor (TFET) is gaining recognition and provide solution for Integrated Circuit (IC) design with low power. This is due to TFET's carrier transportation scheme, which utilizes inter-band tunneling of carriers, and its fabrication similarity to MOSFET. TFET presents itself as a widely adopted device structure that can overcome the limitations of MOSFETs. However, TFETs suffer from poor DC and Radio Frequency (RF) performance, mainlydue to minority carrier transport and physical doping, which forms an abrupt junction in nanoscale devices due to RDFs. The junction-less device structure presents a viable solution to these issues without sacrificing DC parameters, even at high-frequency. Furthermore, the nanotube structure of TFET effectively reduces the Subthreshold Swing (SS) and leakage current due to better controllability of channel. The gate-all-around structure of nanotube TFET improves the surface potential distribution over the channel region, not only enhancing the DC characteristics of TFET but also improving the high-frequency parameters. The core gate Nano Tube (NT)-TFET is a promising device structure for exploring its application in the field of biomedical science as a biosensor. The proposed core gate nanotube structure provides a larger surface area for immobilizing biomolecules in the cavity, thus improving sensitivity analysis. This work proposes the utility of a novel core gate NT-TFET as a biosensor for detecting label-free biomolecules and DNAs. In this design, the detection capability of biosensor is improved, and the detection processes are investigated by high-frequency parameters of the proposed twin cavity dual metal NT-TFET biosensor. This study demonstrates the sensitivity analysis of biosensor based on transit time and device efficiency, which are two critical high-frequency parameters. This approach results in a biosensor with a lower annealing budget, making it more cost-effective and with comparatively highersensitivity

Reduction of variation and leakage in wide fan-in OR Logic domino gate

In this paper, a novel domino gate is proposed to decrease the process variability and leakage current with enhanced noise margin for wide fan-in OR logic. The process variation is decreased by reducing the transconductance of the keeper transistor, whereas the subthreshold leakage current is decreased by redesigning the evaluation network. In addition, a keeper-controlled network is developed to control the switching activity of keeper which eventually reduces the power dissipation. Further, extensive analysis of reliability is accomplished against the process, voltage, and temperature. Further, 64-word*32bit Read ported register file is designed to show the supremacy of proposed domino gate over the conventional domino. All proposed circuits are designed, simulated and verified using SPECTRE simulator in CADENCE VIRTUOSO at 45 nm CMOS technology node. The results reveal that power and delay variability are reduced by 55% and 57%, whereas noise margin is improved by 74% with respect to reported conventional domino. Hence, the analysis suggests that proposed domino circuit can be useful to implement deep submicron low power VLSI circuits.

Improved RF-DC characteristics and reduced gate leakage in GaN MOS-HEMTs using thermally grown Nb2O5 gate dielectric

This work demonstrates the improvement in DC and RF characteristics and a reduction in the gate leakage current for thermally grown Nb2O5 as a gate dielectric in AlGaN/GaN metal–oxide–semiconductor high electron-mobility transistors (MOS-HEMTs). The MOS-HEMTs with an amorphous 10 nm thick Nb2O5 as the gate dielectric show a reduced gate leakage current of 10−9 A mm−1. Nb2O5 thin film creates a tensile strain in the AlGaN layer, enhancing the density of two-dimension electron gas (2-DEG). The performance of the device also improves in terms of saturation drain current, peak transconductance, subthreshold swing, and unity current gain frequency. An increase in the source-to-drain ON/OFF current ratio to 108 and a significant reduction in the subthreshold leakage current by at least two orders of magnitude are measured compared to the control HEMTs.

A Method for Leakage Current and Power Reduction of Buffer in 65-nm CMOS Technology Based on the Pileup-Effect

In small-size Complementary Metal Oxide Semiconductor (CMOS) technology, the size of Very Large-Scale Integration (VLSI) below 90nm becomes higher and higher due to the enhancement of the short channel effect of transistors. CMOS Buffer is a very common circuit unit in VLSI. In this paper, a Pileup effect transistor (PET) is proposed to reduce the subthreshold leakage current of the CMOS buffer. The main principle of PET technology is to reduce the voltage difference between gate and source and the voltage difference between drain and source by lowering the voltage of source so as to reduce the subthreshold leakage current. Through simulation-based on Cadence and Taiwan Semiconductor Manufacturing Company (TSMC) N65 library, PET technology can reduce leakage current power consumption by about one-twelfth of the original while maintaining the function of the original CMOS buffer. PET technology has also been found to reduce current consumption in the transition state by about 40%.

A Dual-Drain Vertical Tunnel FET with Improved Device Performance: Proposal, Optimization, and Investigation

In this manuscript, a dual-drain Vertical Tunnel FET structure is proposed and investigated for the first time. The simulation outcomes clearly manifest that reduction in channel thickness, which has inadequate impact on the tunneling region, significantly improves numerous DC parameters of the proposed device including subthreshold swing, on-state current and current-switching ratio by enhancing the band-to-band tunneling of the charge carriers at source/channel interface caused by enlarged electric field. In order to make the proposed device suitable for low power applications, dielectric material is incorporated in between two drain/channel interfaces to reduce the subthreshold leakage current. A detailed investigation is carried out to determine the influence of varying device footprints on various electrical parameters and accordingly, the optimized device performance is achieved. TCAD-based simulation results reveal that a considerably low subthreshold swing of 18 mV decade−1 along with a high current-switching ratio of can be achieved with optimum geometric dimension of design parameters i.e., gate-oxide, source and channel. Further, the performance of the proposed device is compared with various existing TFET structures and found to be superior in terms of current switching ratio, average subthreshold swing and turn-on voltage. The probable fabrication process flow is also discussed for the proposed device and based on the proper benchmarking, it is revealed that improvement in the parameters like low-output voltage, peak overshoot and rise time defining the switching characteristics of an inverter makes the proposed device more suitable for digital circuit-based applications.

A compact weak PUF circuit based on MOSFET subthreshold leakage current

A compact weak PUF circuit based on MOSFET subthreshold leakage current

Performance analysis of silicon nanotube dielectric pocket Tunnel FET for reduced ambipolar conduction

This work presents a novel structure of Nanotube Tunnel FET in which a high-k dielectric pocket is placed at the drain side to improve DC performance of the device. Using 3D TCAD simulation, it is shown that when a dielectric pocket (DP) is inserted at partially scaled drain region of Nanotube Tunnel FET at channel-drain interface then tunneling width at the output tunneling interface attains a maximum value for an optimum length and diameter of DP (i.e., 30 and 3 nm, respectively) which eventually reduces the ambipolar current up to a large extent. Furthermore, the subthreshold leakage current is also found to be reduced with the inclusion of DP in Nanotube Tunnel FET, thereby improving the current switching ratio (ION/IOFF). Additionally, the impact of varying k-value of DP on various DC parameters of the proposed device is demonstrated in this work and it is found that DP with high k-value reduces the ambipolar and subthreshold leakage current more as compared to the low-k DP. Moreover, the inclusion of DP dose not degrade the ON-state performance of Nanotube Tunnel FET as it has no significant impact on the rate of charge carriers tunneling through channel-drain interface during On-state.

5-nm Gate-All-Around Transistor Technology With 3-D Stacked Nanosheets

A comprehensive computational study of gate-all-around (GAA) devices with 3-D stacked silicon nanosheets (also known as nanoribbons or nanowires) is presented in this article. Technology development guidelines are provided for low-power applications in 5-nm CMOS technology node and beyond. The 3-D stacked nanosheet devices lower the subthreshold swing, drain-induced barrier-lowering, and subthreshold leakage current by up to 20.75%, 38.89%, and 88.53%, respectively, when compared to a silicon-on-insulator (SOI) FinFET with 5-nm physical gate length and identical silicon area at <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {DD}} = {0.6}$ </tex-math></inline-formula> V and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${T} = {80}\,\,^{\circ }\text{C}$ </tex-math></inline-formula> . The voltage gain of a minimum-sized CMOS inverter is increased by up to 157% with the 3-D stacked nanosheet devices, thereby providing robust operation with wider noise margins when compared to the SOI-FinFET technology. Furthermore, by scaling the supply voltage to 0.49 V, the energy consumption of a CMOS inverter is reduced by 53.81% with the GAA 3-D stacked nanosheet devices while providing similar output transition speed when compared to the SOI-FinFET technology.

On-chip leakage current variation measurement using external-reference-free current-to-time conversion for densely placed MOSFETs

This paper proposes a time-domain leakage current measurement circuit that uses an external-reference-free current-to-time conversion. Our proposed current-to-time converter (CTC) utilizes a dual inverter-based conversion to provide a stable reference. We share the CTC among the devices under test (DUTs) for accurate characterization of variation. Our CTC, along with a tree-based switch structure, allows us to densely place and route the DUT transistors using a cell-based design flow similar to a digital circuit design. We demonstrate our circuit by measuring subthreshold leakage currents of 256 minimum sized nMOSFETs in a 65 nm bulk low-power CMOS process. We could successfully extract the variations in subthreshold coefficient and subthreshold leakage current at different temperatures. Our circuit is also robust to supply voltage fluctuation making the circuit suitable for accurate characterization of MOSFET parameters for subthreshold operation.

Differential Aging Sensor Using Subthreshold Leakage Current to Detect Recycled ICs

Electronic system components can fall prey to counterfeiting via untrustworthy parties in the semiconductor supply chain, which has established a worldwide span to reduce costs, time to market, and increase productivity. Recently, integrated circuits (ICs) counterfeiting has threatened systems security and reliability that utilize ICs in all domains. This article focuses on the most counterfeited area—recycled and remarked ICs—and aims to develop a technique to distinguish between new and used digital ICs based on an aging sensor mechanism. Aging sensors have been studied based on path-delay fingerprinting and ring oscillators (ROs) frequency degradation, but their resolution requires further development to accurately detect short usage. This study proposes a novel differential aging sensor to measure the discharge time ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\tau {{{dv}}}$ </tex-math></inline-formula> ) increase that depends on the subthreshold leakage current due to aging with two on-chip designs. Simulations were conducted using the GlobalFoundries (GF) 22 nm for aging with bias temperature instability and hot carrier injection (HCI) combined. The results show that the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\tau {{{dv}}}$ </tex-math></inline-formula> increase is 14.72% after 15 days of usage and increases to 60.49% after three years. This further increases at higher temperatures; the highest simulated temperature ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$125~^{\circ }\text{C}$ </tex-math></inline-formula> ) <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\tau {{{dv}}}$ </tex-math></inline-formula> increases by 55.93% after 15 days and 310.17% after three years. The proposed method also outperformed the traditional frequency degradation-based aging estimation method, which at nominal temperature is found to be 5.00% after 15 days and 23.68% after three years. Therefore, discharge time is a sensitive indicator for aging, surpasses frequency in detecting previous usage and is robust against process, voltage, and temperature variations (PVTs).

Magnetic sensitivity modeling of dual gate MOS transistor

In this paper, the magnetic field effect on the carrier transport phenomenon in the double gate metal-oxide-semiconductor field-effect transistor (MOSFET) has been investigated. This is done by exploring the Lorentz force and the behavior of a semiconductor subjected to a constant magnetic field. The magnetic field modulates the electrons position and density as well as the potential distribution in the case of silicon tunnel tunneling field-effects (FETs). This modulation impacts the device electrical characteristics such as ON current (I&lt;sub&gt;ON&lt;/sub&gt;), subthreshold leakage current (IOF), threshold voltage (V&lt;sub&gt;T&lt;/sub&gt;), magneto-transconductance (g&lt;sub&gt;mm&lt;/sub&gt;) and output magneto-conductance (gm&lt;sub&gt;DS&lt;/sub&gt;). In addition, a hall voltage (V&lt;sub&gt;H&lt;/sub&gt;) is induced and modulated by the magnetic field. It has been observed that this voltage influences the effective applied gate voltage. It has been observed that the threshold voltage variations induced by the magnetic field is of paramount importance and affects the device switching properties both speed and power dissipation, noted that the threshold voltage VT and (Ion/Iof) ratio are reduced by 10&lt;sup&gt;-3&lt;/sup&gt;V and 10&lt;sup&gt;2&lt;/sup&gt; for a magnetic field of ±6 and ±5.5 Tesla, respectively. We have simulated the different behavior in the channel, mainly doping concentration, potential distribution, conduction and valence bands, total current density, total charge density, electric field, electron mobility, and electron velocity.