Studying the Performance of Underlap GAA-FET

Abstract

Abstract: This paper investigates the performance of underlap Gate-All-Around Field Effect Transistor (GAA FET) of 22nm gate length and evaluates the short channel performance of the device. Underlap GAA FET structure can be utilized to increase the drive current of the nanowire devices. In this work, underlap rectangular GAA FET is designed by extension of underlap regions on source/drain of GAA FET to increase the performance. This underlap device is increasing the capacitances by adding the fringing capacitances to parasitic capacitances which increases the fringing field from gate electrode to underlap regions. In this also investigating the electrical parameters on various performance metrics like threshold voltage (Vth), ON current (ION), OFF current or subthreshold leakage current (IOFF), ON-OFF current ratio (ION/IOFF) and short channel effects such as Subthreshold slope (SS) and DIBL (Drain Induced Barrier Lowering) of underlap GAA FET are systematically evaluated and analysed. In the present study, GAA FET and underlap GAA FET device performances are investigated through ATLAS device simulator from Silvaco.