Design and Analysis of Nanoscaled Recessed-S/D SOI MOSFET-Based Pseudo-NMOS Inverter for Low-Power Electronics

Anjali Priya,Nilesh Anand Srivastava,Ram Awadh Mishra

doi:10.1155/2019/4935073

Anjali Priya, Nilesh Anand Srivastava + Show 1 more

Open Access

https://doi.org/10.1155/2019/4935073

Copy DOI

Abstract

In this paper, a comparative analysis of nanoscaled triple metal gate (TMG) recessed-source/drain (Re-S/D) fully depleted silicon-on-insulator (FD SOI) MOSFET has been presented for the design of the pseudo-NMOS inverter in the nanometer regime. For this, firstly, an analytical modeling of threshold voltage has been proposed in order to investigate the short channel immunity of the studied device and also verified against simulation results. In this structure, the novel concept of backchannel inversion has been utilized for the study of device performance. The threshold voltage has been analyzed by varying the parameters of the device like the ratio of metal gate length and the recessed-source/drain thickness for TMG Re-S/D SOI MOSFET. Drain-induced barrier lowering (DIBL) has also been explored in terms of recessed-source/drain thickness and the metal gate length ratio to examine short channel effects (SCEs). For the exact estimation of results, the comparison of the existing multimetal gate structures with TMG Re-S/D SOI MOSFET has also been taken under study in terms of electrostatic performance, i.e., threshold voltage, subthreshold slope, and on-off current ratio. These structures are investigated with the TCAD numerical simulator from Silvaco ATLAS. Furthermore, for the first time, TMG Re-S/D FD SOI MOSFET-based pseudo-NMOS inverter has been designed to observe the device performance at circuit levels. It has been found that the device offers high noise immunity with optimum switching characteristics, and the propagation delay of the studied circuit is recorded as 0.43 ps.

Highlights

Incorporation of new technologies is going to be more crucial in the coming era of CMOS devices [1, 2]
The fin structure was found to be more complex as compared to fully depleted siliconon-insulator (FD SOI) MOSFETs. e leakage and power consumption are drastically reduced by the use of the FD SOI structure [5,6,7]
In the ATLAS simulation, different types of the physical model have been used like field-dependent mobility mode (FLDMOB), concentration-dependent mobility mode (CVT), and Fermi-Dirac statistical model. e doping profile is uniform. e device parameters have been chosen as per the ITRS roadmap. e device channel length (L) is 90 nm, and it has been varied from 20 nm to 300 nm in order to evidence the scaling challenges. e front oxide thickness is considered as 2 nm, buried oxide thickness as 200 nm, silicon channel thickness of 10 nm, and Re-S/D thickness of 30 nm. e studied MOSFET is characterized with uniform source/drain concentration (Nd) of 1020 cm−3 and low bulk doping (Nsub) of 1015 cm−3

Summary

Introduction

Incorporation of new technologies is going to be more crucial in the coming era of CMOS devices [1, 2]. Various technologies have been reported recently regarding the improvement in the device performance at nanometre nodes such as FinFET, FD SOI, recessed-source and drain, and gate engineering [4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20]. In Re-S/D-based device, the depth of source and drain is expanded in the buried insulated layer. It reduces capacitances and gives better drive current [11]

Methods

Results

Conclusion