Simulation of High–<I>κ</I> Dielectrics in Counter Doped Double Gate Metal Oxide Semiconductor Field Effect Transistors

Abstract

With the continued scaling of the SiO 2 thickness below 2 nm in Double Gate MOSFET devices, a large direct-tunneling current flows between the gate electrode and silicon substrate is highly affecting device performance. Therefore, higher dielectric constant materials are desirable for reducing the gate leakage while maintaining transistor performance for very thin dielectric layers. The counter doped (p-type) Double Gate MOSFETs with high-κ gate dielectric material is modeled to obtain the transport characteristics, DIBL, I on /I off ratio, threshold voltage and subthreshold leakage current. Reduction of short channel effects are observed in counter doped (p-type) DG MOSFET with high-κ dielectrics. Drain induced barrier lowering (DIBL) is reduced to ≈25%, subthrehold leakage current is decreased to ≈50%, I on /I off ratio is increased to ≈75% and threshold voltage (V t ) is increased to ≈6% in 1 nm dielectric thickness T ox . Results show that counter doped DG MOSFETs with high-κ gate dielectric material is an effective method to reduce the short channel effects.