Study of Scaling Limits of Multi-Gate Fets (Finfet) With High-K Dielectric

Abstract

Scaling of Multi-Gate FETs (FinFETs) to sub nanometer has seen several challenging problems such as short channel effects which significantly affect the device performance and huge off-state power leakage. High-k dielectric materials had always been looked at as a potential replacement to the conventional SiO2 to increase gate control over the channel which could be a possible solution. This paper examines the impact of scaling FinFETs with varying geometric conditions in the presence of high-k gate dielectrics oxide layer, and further demonstrate conflicting technical trade-off that emerges from short channel effects due to different oxide materials. The electric field distribution, carrier density and mobility of the FinFETs subsequent to miniaturization were also studied. A 3D model of the device is created and simulated using TiberLab and Nanohub to observe the carrier density and mobility in the device as well as the electric field created within the device. Short channel effects specifically drain induced barrier lowering (DIBL) and gate induced drain lowering (GIBL) were also analyzed. The overall results show that although high-k dielectric gate oxide has some drawbacks, it still outperforms SiO2 overall as a gate oxide material and proven to be a solid solution to mitigate short channel effect. The Ion/Ioff for the HfO2-based device increases by 90% as compared to a SiO2-based device. However, it was evident that the threshold voltage had increase slightly from 0.13 V to 0.26 V when the dielectric was changed from SiO2 to HfO2.