5-nm Gate-All-Around Transistor Technology With 3-D Stacked Nanosheets

Abstract

A comprehensive computational study of gate-all-around (GAA) devices with 3-D stacked silicon nanosheets (also known as nanoribbons or nanowires) is presented in this article. Technology development guidelines are provided for low-power applications in 5-nm CMOS technology node and beyond. The 3-D stacked nanosheet devices lower the subthreshold swing, drain-induced barrier-lowering, and subthreshold leakage current by up to 20.75%, 38.89%, and 88.53%, respectively, when compared to a silicon-on-insulator (SOI) FinFET with 5-nm physical gate length and identical silicon area at <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {DD}} = {0.6}$ </tex-math></inline-formula> V and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${T} = {80}\,\,^{\circ }\text{C}$ </tex-math></inline-formula> . The voltage gain of a minimum-sized CMOS inverter is increased by up to 157% with the 3-D stacked nanosheet devices, thereby providing robust operation with wider noise margins when compared to the SOI-FinFET technology. Furthermore, by scaling the supply voltage to 0.49 V, the energy consumption of a CMOS inverter is reduced by 53.81% with the GAA 3-D stacked nanosheet devices while providing similar output transition speed when compared to the SOI-FinFET technology.