Subthreshold Leakage Current Research Articles

Degradation in Pmosfet during Off-State Stress

Degradation of P-channel MOSFET during off-state stress with ac bias has been experimentally investigated. Sub-threshold leakage increased after off-state with ac bias. It was caused by hot electron injection during off-state. With varying source voltage, the degradation during off-state stress with ac bias was more severe than off-state stress with dc bias. Degradation impact was the same as hot electron induced punch-through (HEIP) during on-state. It was observed that subthreshold leakage current of pMOSFET increased and standby current became serious. Gate length, tap width, doping concentration at source/drain extension, operation temperature and operation frequency, respectively, were evaluated and the degradation modeling has been introduced in our paper. Figure 1

Simulation of a Nanoscale SOI TG n-FinFET

The objective of this work is to study the electrical characteristics of a nanoscale SOI Tri-Gate n-channel fin field-effect transistor (FinFET) structure with 8 nm gate length using Semiconductor TCAD tools. ATLASTM tools are computer programs which allow for the creation, fabrication, and simulation of semiconductor devices in three dimensions with different models under consideration. The drain current, transconductance, threshold voltage, subthreshold slope, leakage current, drain induced barrier lowering, and IOn/IOff current ratio are analyzed in the various biasing configuration. In addition, FinFET device with a high value of gate dielectric constant exhibits much better performance compared to the Si3N4 dielectric material, which is desirable for high performance low-power/low-voltage applications. It is found that increasing the high-k value was beneficial in reducing the subthreshold slope, DIBL, and leakage current. General Terms Integrated Circuit, VLSI, FinFET Device Modeling.

Hot-Electron Degradation of AlGaN/GaN High-Electron Mobility Transistors During RF Operation: Correlation With GaN Buffer Design

Comprehensive RF stress-test campaign has been performed over AlGaN/GaN high-electron mobility transistor employing different GaN buffer designs, including unintentional doping, carbon doping and iron doping. No signature of gate-edge degradation has been found, and good correlation emerges between the buffer composition, subthreshold leakage current, and permanent degradation of the RF performance. The degradation mechanism, more pronounced in devices with parasitic buffer conductivity, involves the generation of additional deep trap states, the worsening of the dynamic current collapse, and the subsequent degradation of RF output power.

Analysis of leakage current and power reduction techniques in FinFET based SRAM cell

In this paper we have proposed a FinFET based 6T static random access memory (SRAM) cell. FinFET devices can be used to improve the performance, reduce the leakage current and power dissipation. The purpose of this article is to reduce the leakage current and leakage power of FinFET based 6T SRAM cell using various techniques in 45 nm technology. FinFET based 6T SRAM cell has been designed and analysis has been carried out for leakage current and leakage power. For low power memory design the most important problem is to minimize the sub-threshold leakage current and gate leakage current. This work introduces a technique based on threshold voltage, gate oxide thickness and power supply setting together to minimize sub-threshold and gate leakage current of 6T SRAM cell. These simulation results are carried out using Cadence Virtuoso Tool at 45 nm technology.

IJIREEICE - Electrical, Electronics, Instrumentation and Control

3 Abstract: As technology scales, sub-threshold leakage currents grow exponentially and become an increasingly large component of total power dissipation. To improve performance of the MOSFETs, doping profile of channel is changed. In this paper, we present comparison of uniform doping (UD), horizontal high source side doping (HHSS) &horizontal high drain side doping (HHDS) and draw the various characteristics i.e. channel electric field, surface potential & sub threshold leakage current .our results show that the horizontal high source sidedoping exhibit excellent properties not only higher mobility but also hot electron degradation improvement and better reliability. Therefore, refer to the results, horizontal high source side doping structure has superior performances in comparison with uniform and horizontal high drain side doping (HHDS). All the device simulations are performed using SILVACO Atlas device simulator.

Incorporating Process Variations Into SRAM Electromigration Reliability Assessment Using Atomic Flux Divergence

Electromigration (EM) greatly affects the long-term reliability of VLSI chips. Not only power/ground lines but also bitlines of SRAM arrays may be damaged by EM. In this paper, we analyze current flow on SRAM bitline, demonstrate that it may suffer EM due to the pulsed dc pattern, and conclude that bitline's EM reliability can dramatically be worsened by process variation due to a significant increase of subthreshold leakage current. We statistically model the effects of process variation that includes both transistor parameter fluctuation and interconnect line roughness, propose an atomic flux divergence-based current conversion scheme for applying Blech criterion, and develop a procedure for preventing EM failure by modifying the width of bitlines. Considering the effect of bitline width modification on cell stability and performance, we propose a tradeoff between functional and EM failures and indicate an optimal bitline width that maximizes the yield of SRAM arrays.

Characteristic analysis of a novel low power 10T SRAM cell during read and write operations

This paper focuses on characteristic analysis of a novel 10T SRAM cell. In the proposed cell two voltage sources VS1 and VS2 are used, one of which connected with the bit line and the other connected with the bitbar line, respectively, for reducing the voltage swing during the switching activity. This reduction in voltage swing causes less dynamic power dissipation during switching activity. Two stack transistors ST1 and ST2 are also connected in the pull-down paths. Due to the stack effect in the pull-down transistors in OFF condition sub-threshold leakage current is reduced and this causes reduction of static power dissipation. Simulation has been done in 45nm CMOS technology with 0.7 volt power supply with the help of Microwind 3.1 software. The simulation results of power dissipation, noise margin, power delay product and current leakage during read/write operation have been determined and compared to those of other existing SRAM cells.

Quantum Transport Simulations of CNTFETs: Performance Assessment and Comparison Study with GNRFETs

In this paper, we explore the electrical properties and high-frequency performance of carbon nanotube field-effect transistors (CNTFETs), based on the non-equilibrium Green’s functions (NEGF) solved self - consistently with Poisson’s equations. The calculated results show that CNTFETs exhibit superior performance compared with graphene nanoribbon field-effect transistors (GNRFETs), such as better control ability of the gate on the channel, higher drive current with lower subthreshold leakage current, and lower subthreshold-swing (SS). Due to larger bandstructure-limited velocity in CNTFETs, ballistic CNTFETs present better high-frequency performance limit than that of Si MOSFETs. The parameter effects of CNTFETs are also investigated. In addition, to enhance the immunity against short - channel effects (SCE), hetero - material - gate CNTFETs (HMGCNTFETs) have been proposed, and we present a detailed numerical simulation to analyze the performances of scaling down, and conclude that HMG-CNTFETs can meet the ITRS’10 requirements better than CNTs.

POWER GATING TECHNIQUE USING FinFET FOR MINIMIZATION OF SUB-THRESHOLD LEAKAGE CURRENT

In this paper, a novel power gating method has been proposed with the combination of complementary metal oxide semiconductor (CMOS) logic and FinFET for better sub-threshold leakage current minimization. Sub-threshold leakage currents take the paramount part in overall contribution to total power dissipation which comprises of scaling and power reduction. Power gating technique takes up priority among the different leakage current reduction mechanisms. The novel approach has been applied to a CMOS inverter and a two input CMOS NAND gate. The inverter simulated with high threshold voltage metal oxide semiconductor field effect transistor (MOSFET), VGOT MOSFET and fin field effect transistor (FinFET) as sleep transistor reduces the sub-threshold leakage current by 45.529%, 47.265% and 86.431%, respectively, when compared with inverter in absence of sleep transistor. This proves substantial improvement as compared to the planar CMOS inverter. Further, these techniques applied for a two input NAND gate resulted in reduction of leakage current by 20.536%, 23.955% and 99.942%, respectively.

Hetero-gate-dielectric double gate junctionless transistor (HGJLT) with reduced band-to-band tunnelling effects in subthreshold regime

We propose a hetero-gate-dielectric double gate junctionless transistor (HGJLT), taking high-k gate insulator at source side and low-k gate insulator at drain side, which reduces the effects of band-to-band tunnelling (BTBT) in the sub-threshold region. A junctionless transistor (JLT) is turned off by the depletion of carriers in the highly doped thin channel (device layer) which results in a significant band overlap between the valence band of the channel region and the conduction band of the drain region, due to off-state drain bias, that triggers electrons to tunnel from the valence band of the channel region to the conduction band of the drain region leaving behind holes in the channel. These effects of band-to-band tunnelling increase the sub-threshold leakage current, and the accumulation of holes in the channel forms a parasitic bipolar junction transistor (n–p–n BJT for channel JLT) in the lateral direction by the source (emitter), channel (base) and drain (collector) regions in JLT structure in off-state. The proposed HGJLT reduces the subthreshold leakage current and suppresses the parasitic BJT action in off-state by reducing the band-to-band tunnelling probability.

Device characteristics of the thin-film silicon-on-insulator power MOSFETs at high temperatures

In this paper, we report high-temperature (up to 573 K) device characteristics, such as subthreshold characteristics, threshold voltage, on-resistance, breakdown characteristics, breakdown voltage, and leakage current, for the thin-film silicon-on-insulator power MOSFETs based on experimental results. The subthreshold slope, on-resistance, and leakage current increase with increasing temperature. The breakdown voltage and threshold voltage decrease with increasing temperature. Dependences of these characteristics on the channel and drift lengths are also analyzed.

Interleaving Test Algorithm for Subthreshold Leakage-Current Defects in DRAM Considering the Equal Bit Line Stress

Since the minimum feature size of dynamic RAM has been down-scaled, several studies have been carried out to determine ways to protect cell data from leakage current in many areas. In the field of testing, more appropriate test algorithms are required to detect weak cells with leakage-current sources. In this paper, we propose an interleaving test algorithm that takes into account the equal bit-line stress regardless of the cell location. The proposed test algorithm allows screening of weak cells that cannot hold cell data due to the subthreshold leakage current. During the stress period, the algorithm can also detect other leakage currents. This paper presents the maximum stress differences according to the cell location, and determines the influence of the refresh operation on the maximum stress time. Therefore, this paper suggests a correlation between the refresh and read time to give maximum stress time.

Normally-OFF Al2O3/AlGaN/GaN MOS-HEMT on 8 in. Si with Low Leakage Current and High Breakdown Voltage (825 V)

We report recessed-gate Al2O3/AlGaN/GaN normally-OFF metal–oxide–semiconductor high-electron-mobility transistors (MOS-HEMTs) on 8 in. Si. The MOS-HEMTs showed a maximum drain current of 300 mA/mm with a high threshold voltage of +2.4 V. The quite low subthreshold leakage current (∼10−8 mA/mm) yielded an excellent ON/OFF current ratio (9 × 108) with a small, stable subthreshold slope of 74 mV/dec. An atomic-layer-deposited Al2O3 layer effectively passivates, as no significant drain current dispersions were observed. A high OFF-state breakdown voltage of 825 V was achieved for a device with a gate-to-drain distance of 20 µm at a gate bias of 0 V.

DUAL THRESHOLD VOLTAGE DOMINO ADDER DESIGN WITH PASS TRANSISTOR LOGIC USING STANDBY SWITCH FOR REDUCING SUB-THRESHOLD LEAKAGE CURRENT

Standby switch can strongly turn off all the high threshold voltage transistors, which enhances the effectiveness of a dual threshold voltage CMOS technology to reduce sub-threshold leakage current. Sub-threshold leakage currents are especially important in burst mode type integrated circuits where the system is in an idle mode in the majority of the time. The standby switch allows a domino system to enter and leave a low leakage standby mode within a single clock cycle. In addition, we combine domino dynamic logic with pass transistor XNOR and pass transistor NAND gates to achieve logic 1 output during its precharge phase without affecting circuits operation in its evaluation and standby phase. The required process for dual threshold voltage circuit configuration involves only one additional ion implant step to provide an extra threshold voltage. SPICE simulation for our proposed circuits is made using a 0.18 μm CMOS processes from TSMC, with 10 fF capacitive loads in all output nodes, and parameters for typical process corner at 25°C. Layout is designed, wafer is fabricate and measured. The measurement results of fabricated chips are listed and verify that our designed 8-bit carry look-ahead adders (CLAs) reduced power consumption and propagation delay time by more than 15% and around 20%, respectively, when compared with the prior work.

Analyzing the Impact of Bootstrapped ADC with Augmented NMOS Sleep Transistors Configuration on Performance Parameters

This paper represents an efficient bootstrapped analog to digital converter with augmented NMOS sleep transistors. The newly designed MOS-based bootstrapped circuit is implemented to provide controlled input supply for analog to digital converter to develop the enhancing capability of circuit. This will reduce the effective leakage of the circuit. In the second stage, the NMOS sleep transistors are augmented as pull-up and pull-down transistors. Due to augmentation of transistors, controlled power supply ( $$V_{\mathrm{DD}})$$ V DD ) is obtained. Because of this, current driving capability in MOS transistors is improved and minimum sub-threshold leakage current is formed. Due to this, reduction of leakage power dissipation occurs much effectively. The whole simulation has been done at 45 nm (nanometer) technology. It is realized that the leakage power is reduced till 50 % approximately and delay performance is improved. It means that speed is improved using bootstrapped circuit with augmented sleep transistors NMOS. In this paper, different consecutive designs with Analog to Digital converter are represented.

Performance and Reliability Characterization of 1200 V Silicon Carbide Power MOSFETs and JFETs at High Temperatures

1200 V Silicon Carbide (SiC) Metal-Oxide-Semiconductor Field Effect Transistors (MOSFETs) and Junction Field Effect Transistors (JFETs) have been characterized at high operational temperatures. For packaged JFETs obtained from a collaborating manufacturer, the threshold shift (ΔVT) was measured under both static and dynamic voltage stress and, in all cases, was less than 2 mV, which is within the measurement margin of error. Temperatures up to 250°C and stress times as long as 200 hours were evaluated. As a comparison, commercially available SiC MOSFETs demonstrated shifts of up to 300 mV after 30 minutes of static gate stress at 175°C. In addition, results from unpackaged JFET die at temperatures up to 525°C show ΔVT values of less than 10 mV for all stress conditions. Although VT remained unchanged for the duration of the test for both static and dynamic stress conditions, under dynamic stress conditions the JFET packaged parts demonstrated a linear increase in sub-threshold leakage current of around 15.6 nA per hour; in contrast, the MOSFET devices showed an exponential increase in sub-threshold leakage under dynamic stress. The increase in sub-threshold leakage current could be recovered temporarily, but long-term behavior was consistent with cumulative damage.

Reduction of defect formation in amorphous indium-gallium-zinc-oxide thin film transistors by N2O plasma treatment

An abnormal sub-threshold leakage current is observed at high temperature in amorphous indium-gallium-zinc-oxide thin film transistors (a-IGZO TFTs). This phenomenon occurs due to a reduced number of defects in the device's a-IGZO active layer after the device has undergone N2O plasma treatment. Experimental verification shows that the N2O plasma treatment enhances the thin film bonding strength, thereby suppressing the formation of temperature-dependent holes, which are generated above 400 K by oxygen atoms leaving their original sites. The N2O plasma treatment devices have better stability performance than as-fabricated devices. The results suggest that the density of defects for a-IGZO TFTs with N2O plasma treatment is much lower than that in as-fabricated devices. The N2O plasma treatment repairs the defects and suppresses temperature-dependent sub-threshold leakage current.

A Novel High Performance Dual Threshold Voltage Domino Logic Employing Stacked Transistors

Among the assorted logic styles used in fostering the integrated circuits, the domino logic styles offers higher speed and smaller transistor count as compared to the static cmos circuits. However the domino logic suffers from lower noise immunity and higher power dissipation due to the problem of charge sharing and sub-threshold leakage currents. In this paper some of the earlier proposed techniques to reduce the power consumption of the domino circuits like Dual threshold voltage (DTV) and Dual threshold voltage–voltage scaling(DTVS) have been analyzed. A novel stacked transistors Dual threshold voltage (ST-DTV) approach which deploys DTV technique with stacked transistors together with a voltage regulated static keeper is analyzed to abate the total power dissipation of the circuit together with a better Power delay product (PDP). The ST-DTV design is tested on a 3input OR gate and a 4x1 multiplexer at 90nm technology on multiple voltages and frequencies. Tanner tool EDA v13.0 is used for simulation. General Terms Power Consumption, Power Delay Product.

The Cause of Subthreshold Leakage Currents Induced by Nucleons and Ions in Power MOSFETs

Additional evidence is presented and discussed on the mechanism for the subthreshold leakage currents induced in power MOSFETs by single nucleon and ion interactions. The new evidence excludes microdose in gate oxides and instead points to microdose in field/edge oxides.

Pass transistor with dual threshold voltage domino logic design using standby switch for reduced subthreshold leakage current

Dual threshold voltages domino design methodology utilizes low threshold voltages for all transistors that can switch during the evaluate mode and utilizes high threshold voltages for all transistors that can switch during the precharge modes. We employed standby switch can strongly turn off all of the high threshold voltage transistors which enhances the effectiveness of a dual threshold voltage CMOS technology to reduce the subthreshold leakage current. Subthreshold leakage currents are especially important in burst mode type integrated circuits where the majority of the time for system is in an idle mode. The standby switch allowed a domino system enters and leaves a low leakage standby mode within a single clock cycle. In addition, we combined domino dynamic circuits style with pass transistor XNOR and CMOS NAND gates to realize logic 1 output during its precharge phase, but not affects circuits operation in its evaluation and standby phase. The first stage NAND gates output logic 1 can guarantee the second stage computation its correct logic function when system is in a cascaded operation mode. The processing required for dual threshold voltage circuit configuration is to provide an extra threshold voltage involves only an additional implant processing step, but performs lower dynamic power consumption, lower delay and high fan-out, high switching frequencies circuits characteristics. SPICE simulation for our proposed circuits were made using a 0.18µm CMOS process from TSMC, with 10fF capacitive loads in all output nodes, using the parameters for typical process corner at 25°C, the simulation results demonstrated that our designed 8-bit carry look-ahead adders reduced chip area, power consumption and propagation delay time more than 40%, 45% and around 20%, respectively. Wafer based our design were fabricated and measured, the measured data were listed and compared with simulation data and prior works. SPICE simulation also manifested lower sensitivity of our design to power supply, temperature, capacitive load and process variations than the dynamic CMOS technologies.