Incorporating Process Variations Into SRAM Electromigration Reliability Assessment Using Atomic Flux Divergence

Abstract

Electromigration (EM) greatly affects the long-term reliability of VLSI chips. Not only power/ground lines but also bitlines of SRAM arrays may be damaged by EM. In this paper, we analyze current flow on SRAM bitline, demonstrate that it may suffer EM due to the pulsed dc pattern, and conclude that bitline's EM reliability can dramatically be worsened by process variation due to a significant increase of subthreshold leakage current. We statistically model the effects of process variation that includes both transistor parameter fluctuation and interconnect line roughness, propose an atomic flux divergence-based current conversion scheme for applying Blech criterion, and develop a procedure for preventing EM failure by modifying the width of bitlines. Considering the effect of bitline width modification on cell stability and performance, we propose a tradeoff between functional and EM failures and indicate an optimal bitline width that maximizes the yield of SRAM arrays.