Reduction of variation and leakage in wide fan-in OR Logic domino gate

Abstract

In this paper, a novel domino gate is proposed to decrease the process variability and leakage current with enhanced noise margin for wide fan-in OR logic. The process variation is decreased by reducing the transconductance of the keeper transistor, whereas the subthreshold leakage current is decreased by redesigning the evaluation network. In addition, a keeper-controlled network is developed to control the switching activity of keeper which eventually reduces the power dissipation. Further, extensive analysis of reliability is accomplished against the process, voltage, and temperature. Further, 64-word*32bit Read ported register file is designed to show the supremacy of proposed domino gate over the conventional domino. All proposed circuits are designed, simulated and verified using SPECTRE simulator in CADENCE VIRTUOSO at 45 nm CMOS technology node. The results reveal that power and delay variability are reduced by 55% and 57%, whereas noise margin is improved by 74% with respect to reported conventional domino. Hence, the analysis suggests that proposed domino circuit can be useful to implement deep submicron low power VLSI circuits.