Abstract
In recent years, wide fan-in OR logic domino circuits have become essential parts to implement resister files, PLA, L1 latches, superscalar microprocessors, wide Mux/De-Mux flip-flop, etc. These memory elements require a type of wide fan-in OR logic domino circuit that has minimum leakage current, low power dissipation and enhanced noise margin. To address this issue, numerous research groups are working on this aspect by using different leakage minimization and noise immunity improvement techniques. Advanced techniques, such as stacking effect, isolating output to the PDN, and keeper controlling network, etc., are very efficient to escalate the noise immunity and minimize the leakage current. Moreover, FINFET and carbon nanotube MOSFETs, etc. are also being used to implement the wide fan-in domino circuit. In this chapter, a detailed study is done for methods used by researchers all over the world to improve the performance of wide fan-in OR logic domino circuits in the field of submicron VLSI design. It has been observed that leakage current could be overcome by modifying the evaluation network. Further, noise immunity could be upgraded by modifying the keeper network.
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