Subthreshold Current Model Research Articles

Subthreshold Drain Current Model of Cylindrical Gate All‐Around Junctionless Transistor With Three Different Gate Materials

ABSTRACTA novel subthreshold drain current model has been developed for a cylindrical gate all‐around junctionless transistor with three different gate materials. The proposed device is built with three gate regions of different work functions that effectively reduce the short‐channel effects caused by quantum mechanical effects. The drain current equation is solved for all three operating regions to investigate the device switching characteristics and minimize the drain‐induced barrier lowering (DIBL), velocity saturation, mobility degradation, and tunneling. It is understood that the triple material gate structure enhances the transport efficiency of the device. The proposed analytical model is validated by comparison with Sentaurus TCAD numerical simulator results and good agreement is found to be achieved.

A ballistic model for subthreshold current and threshold voltage of the dual-material-gate nanosheet MOSFET

— A ballistic model for subthreshold current of the dual-material-gate (DMG) nanosheet (NS) MOSFET is developed based on the Landauer approach, three-dimensional scaling equation, and the continuity of subthreshold current at the interface between the control gate and screen gate in the channel, The work function difference between the screen gate and control gate can be converted into the new interface-quasi-fermi-potential (IQFP) at the junction between different gate regions. Through the IQFP, the ballistic subthreshold current for DMG NS MOSFET is successfully developed. With the determined subthreshold current, the ballistic threshold voltage can also be achieved by the constant current method. Under the low and high drain voltage corresponding to their IQFPs, the subthreshold behavior is mainly governed by the contact potential and thermal voltage, respectively. Furthermore, Ohm's law regarding ballistic resistance for the DMG NS MOSFET can still be valid in the subthreshold conduction.

All region analytical modeling of 2-D transition metal dichalcogenide FET by considering effect of fringing field and region-wise mobility

In this paper, for the first time an analytical all region model of Transition metal dichalcogenide based FET has been developed to represent the current–voltage characteristics of the device in ultra-short channel regime. Starting from Gauss’s law, Poisson’s equation is formulated and short channel subthreshold current model is developed subsequently. In order to include fringing field effect, the gaussian box is considered for top and bottom oxides along with channel. Next, Velocity saturation model is developed by considering mobile charges due to top-bottom gates and region-wise field dependent mobility in the channel utilizing the drift diffusion approach. Both the models are then unified by finding the natural points of transition from one model to other. The intraband source to drain tunneling has also been incorporated to develop generalized 2-D material based FET model. Veracity of the model has been verified with NEGF simulations for different device parameters and excellent congruence is observed. The effect of the interface trap charge density has also been included in the model and its effects on the transfer characteristics are investigated. • Analytical modeling of I-V characteristics for TMD materials applicable for all channel lengths. • Validation of model with atomistic simulator data for Sub 10 nm channel length. • Effects of double gate and fringing field have been included. • Source to drain tunneling has been included to increase model applicability for any 2D materials.

Analytical subthreshold current model of the dual-material tri-gate (DMTG) MOSFET and its application for subthreshold logic gate

Multi-gate MOSFETs are considered for realizing ultra-low-power circuits due to their superior channel control capability and short channel effect (SCE) resistance. To achieve this goal, it is necessary to establish a suitable compact device circuit model for them. However, current research focuses more on single-material multi-gate MOSFET, and there is no research report on dual-material logic gates. In this work, we develop a subthreshold current model for dual-material tri-gate (DMTG) MOSFET. It is found that the gate metal close to the source can affect the subthreshold characteristics of the transistor to a greater extent. Moreover, combined with the equivalent transistor model, the noise margin (NM) model of the subthreshold inverter composed of DMTG MOSFETs is developed. The nearly equal NM can be obtained by equal NM design (END). An appropriate work function can be selected through END to obtain the optimal NM when designing the inverter. The NM under different device geometric parameters is given, and the simulation result shows that the model accuracy reaches 98%. Finally, the effect of DMTG structure on the device drain induced barrier lowering (DIBL) is given, which effectively reduces DIBL by 42%. These models still remain high accuracy when the device channel length shrink down to 20 nm, which provide the possibility for DMTG MOSFET to be effectively applied to ultra-low-power circuits.

Unconventional VTC of subthreshold inverter with MFMIS negative capacitance transistor: An analytical modelling framework with implications for ultralow power logic design

The present reports an analytical modelling framework to provide insights into subthreshold logic design using metal-ferroelectric-metal–insulator-semiconductor (MFMIS) negative capacitance field effect transistor (NCFET). It is shown that the proposed model is effective in predicting supply voltage (V DD) dependent hysteresis as well as hysteresis-free voltage transfer characteristics (VTC) through the analytically obtained positive (hysteresis-free) and negative (hysteresis) values of gain (−dV O/dV IN) in NCFET based subthreshold inverter. The proposed subthreshold drain current model for NCFET has been extended to obtain closed-form analytical expressions of figures of merit of a subthreshold inverter such as nominal high and low output voltages, threshold logic voltage, and DC gain. The model while successfully capturing characteristics of MFMIS NCFETs is able to predict the occurrence of hysteresis in VTC due to negative differential resistance in the output characteristics of NCFET. Results show that an optimally designed MFMIS NCFET based inverter can achieve similar values of DC gain as exhibited by conventional MOSFET at ∼×(3–6) times lower supply voltages (V DD) along with an improvement in static and dynamic power dissipation. Results showcase an analytical modelling framework and its implications for reducing V DD for ultralow power subthreshold logic design with NCFETs.

Analytical model of subthreshold drain current for nanoscale negative capacitance junctionless FinFET

In this article, an analytical Subthreshold Drain Current model has been developed for Negative Capacitance Junctionless FinFET (NC-JL FinFET). To obtain the subthreshold current model for NC-JL FinFET the drift-diffusion equation is solved by including negative capacitance effect through LK equation and further utilized to attain the expression of subthreshold slope (SS). The influence of the fringing field due to source/drain spacer on the subthreshold current has been included in the model. The model predictions turn out to be in fair agreement with numerical simulation results. The performance of NC-JL FinFET is also examined for different technology nodes. Also, the influence of physical parameters like ferroelectric thickness, gate dielectric constant, fin thickness, spacer length etc. has also been analyzed. Further, the SS is also examined for variations in several device design parameters. It has been revealed that the NC-JL FinFET improves subthreshold current and SS by almost 80% and 16.7%, respectively as compared to JL FinFET.

Mitigating DIBL and Short-Channel Effects for III-V FinFETs With Negative-Capacitance Effects

This paper, based on the IRDS 2022 technology node, investigates the DIBL and short-channel effects for InGaAs negative-capacitance FinFETs (NC-FinFETs) through a theoretical subthreshold drain current model considering key effects including negative capacitance, quantum confinement and source-to-drain tunneling. Due to the impact of negative capacitance on the source-to-drain potential profile, tunneling distance and its drain-bias dependence, the short-channel effects can be substantially improved for InGaAs NC-FinFETs. Our study indicates that, with the larger NC effect of the III-V channel, the gap in DIBL and subthreshold swing between InGaAs and Si FinFETs in the sub-20 nm gate-length regime can become much closer. Our study may provide insights for future supply-voltage/power scaling of logic devices with high-mobility channel.

Junctionless Multiple-Gate (JLMG) MOSFETs: A Unified Subthreshold Current Model to Assess Noise Margin of Subthreshold Logic Gate

With the quasi-3-D scaling equation, quasi-3-D minimum channel potential, and drift-diffusion model, a unified subthreshold current model for junctionless multiple-gate (JLMG) MOSFETs including quadruple-gate (QG), triple-gate (TG), and omega-gate ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Omega \text{G}$ </tex-math></inline-formula> ) devices is developed. With this subthreshold current model, the noise margin (NM) behavior of the subthreshold logic gate composed of JLMG MOSFETs is assessed. With the same cross-sectional area of the devices, the QG MOSFET provides the largest NM among the three devices due to its smallest scaling length. On the contrary, the TG MOSFET with the largest scaling length exhibits the smallest NM. The short-channel-degraded NM behavior can be similarly seen in these devices. In terms of design triangle (DT) of subthreshold logic gate, the QG MOSFET can provide the largest DT as opposed to the smallest one supplied by the TG device. The transistor strength balance (TSB) between p-type and n-type JLMG MOSFETs can be adjusted by tuning the gate work function to implement the optimum NM design. Finally, the impact of random doping fluctuation (RDF) on NM degradation is also discussed in this work.

Subthreshold Current Modeling of Stacked Dielectric Triple Material Cylindrical Gate All Around (SD-TM-CGAA) Junctionless MOSFET for Low Power Applications

Subthreshold Current Modeling of Stacked Dielectric Triple Material Cylindrical Gate All Around (SD-TM-CGAA) Junctionless MOSFET for Low Power Applications

Nanosheet FET: A new subthreshold current model caused by interface-trapped-charge and its application for evaluation of subthreshold logic gate

Based on the quasi-3D potential approach, quasi-3D scaling theory, drift-diffusion model, and equivalent flat-band shift, a new subthreshold current model caused by the interface-trapped-charge is developed for the nanosheet FET. With the subthreshold current Isub, the noise margin (NM) of the subthreshold logic gate composed of nanosheet FET is thoroughly evaluated. It is found that the positive interface-trapped-charge can degrade the high noise margin (NMH) due to its increased/decreased subthreshold current of N-FET/P-FET. On the contrary, the negative interface-trapped-charge can decrease/increase subthreshold current of N-FET/P-FET, which hence deteriorates the low noise margin (NML). Both degradation of the subthreshold current and NM (i.e., ΔIsub and ΔNM) caused by short-channel effects (SCEs) can be well-controlled by the properly selected scaling factor of α. With the minimum scaling factor αmin that allows for the minimum noise margin degradation (ΔNM), the minimum channel length Lmin for the nanosheet FET can be obtained as it is readily applied for the subthreshold logic gate.

An analytical subthreshold current model for ferroelectric SiGe-on-insulator field effect transistor (FSGOIFET)

In this paper, a novel device concept has been presented which integrates ferroelectric gate insulator on SiGe-On-insulator (SGOI) substrate. An analytical subthreshold current model for ferroelectric SGOI field effect transistor (FSGOIFET) has been developed by using 2D Poisson’s equation and Landau–Khalatnikov equation. The explicit expressions for threshold voltage and subthreshold current have been obtained by extending the electrostatic potential model. The other important device parameters such as drain induced barrier lowering, threshold voltage roll-off, subthreshold swing etc have been obtained to quantitatively study the performance of FSGOIFET at shorter channel length. The merits of ferroelectric gate insulator have been demonstrated by comparing all device characteristics of FSGOIFET with those obtained for SGOIFET. An excellent fit of analytical results with simulation results obtained from Silvaco ATLAS TCAD has corroborated the accuracy of the presented model.

A semiphysical current–voltage model with a contact ideality factor for disordered thin-film transistors

A semiphysical current–voltage model for disordered thin-film transistors is presented. In the proposed model, a power-law function is employed to describe the drift current in the above-threshold region while a Fermi–Dirac function-like exponential formula is introduced to describe the diffusion current in the subthreshold region. In particular, this subthreshold current model is more physically meaningful compared with the typical exponential model. In addition, it also contains an ideality factor for the source and drain contacts, explaining the vertical separation of the drain current for different drain voltages in the subthreshold region. Using the proposed approach, analytical expressions are derived, providing good agreement with experimental results in both the linear and saturation regimes.

A New Device-Parameter-Oriented DC Power Model for Symmetric Operation of Junctionless Double-Gate &lt;sc&gt; mosfet&lt;/sc&gt; Working on Low-Power CMOS Subthreshold Logic Gates

Based on the subthreshold current and equivalent transistor models, a new device-parameter-oriented average DC power model average DC power (PDC) for symmetric operation of junctionless double-gate mosfet (JLDGFET) working on the low-power CMOS subthreshold logic gate is developed. Although short-channel effects can increase P DC significantly, the balanced transistor strength will reduce PDC more efficiently by improving the consistency of transistor strength between P-JLDGFET and N-JLDGFET. Being similar to DIBL, the minimum channel length that corresponds to the allowable maximum PDC in designing the low-power logic gate can be determined according to the scaling theory. Although the inverter (INV) may act as the fundamental building unit for the logic circuits due to its least gate counts among INV, nand , and nor , it consumes the most PDC among these logic gates. The minimum DC power PDC,min can be obtained by tuning the gate work-function, which ensures the equal transistor strength between P-JLDGFET and N-JLDGFET. Both of the variability and sensitivity induced by the process parameters are also accounted for in developing PDC model.

Subthreshold Modeling of Tri-Gate Junctionless Transistors With Variable Channel Edges and Substrate Bias Effects

In this paper, subthreshold channel potential, current, swing, threshold voltage, and drain-induced barrier lowering models of short-channel tri-gate junctionless field-effect transistors are presented. The models incorporate the effects of both substrate-induced surface potential and variable edges of channel. The quasi-3-D approach is used for the modeling of minimum of channel potential that is subsequently used in the drift–diffusion equation to obtain the current expression in subthreshold regime. Threshold voltage and subthreshold swing models are also based on the minimum of channel potential. The analytical results are compared with the simulation data obtained using 3-D visual TCAD device simulator from Cogenda Pvt., Ltd.

A Unified Quasi-3D Subthreshold Behavior Model for Multiple-Gate MOSFETs

Based on the quasi-3D potential approach, a unified subthreshold-potential, threshold-voltage, and subthreshold-current model is developed for multiple-gate mosfet s including a quadruple-gate, triple-gate, and omega-gate mosfet . This work indicates that the scaling-length-oriented subthreshold current roll-up Δ I sub and threshold voltage roll-off Δ V th provide the physical insight into well-controlled short-channel effects (SCEs) in terms of effective scaling length λ eff according to the scaling factor. Besides the decreased minimum conducting channel potential Φ C ,min, the smaller scaling-length-induced effective channel width/height ( W eff/ H eff) reflects the smaller effective conducting cross-sectional area, which reduces the subthreshold current degradation due to the increased subthreshold resistance R sub. By accounting for the coupling factor in the quasi-3D potential approach, W eff, H eff, and Φ C ,min will be increased to some extent to decrease R sub, which, hence, degrades the subthreshold behavior more extensively in response to SCEs.

An All-Region I–V Model for 1-D Nanowire MOSFETs

An all-region short-channel MOSFET, model is developed for nanowire semiconductors with 1-D density of states. It is shown that in the quantum capacitance limit, the long-channel saturation current exhibits a ( Vgs − Vt )3/2 dependence on gate voltage. With the velocity saturation effect implemented in the model, the Ids – Vgs characteristics of 1-D MOSFETs are compared to those of 2-D MOSFETs at 10-nm channel length. The above threshold model is joined with a subthreshold current model derived from short-channel solutions to form an I – V model continuous in all regions.

Analytical modeling of subthreshold characteristics of ultra-thin double gate-all-around (DGAA) MOSFETs incorporating quantum confinement effects

In this work, analytical models of subthreshold current and subthreshold swing of short channel ultra-thin double gate-all-around (DGAA) MOSFETs including quantum confinement effects have been proposed. The subthreshold current model is presented using Pao-Sah's double integration formula accounting both drift and diffusion components of the current. Quantum effects arising due to 2-D carrier confinement are incorporated in the model to consider the effective carrier density reduction in ultra-thin channel region. A detailed analysis of charge density calculation using density of states (DOS) method is also done. Further, the virtual-cathode potential has been utilised to model the subthreshold swing of the device. The effect of device design parameters like channel thickness, oxide thickness, gate length etc. on subthreshold characteristics has been extensively studied. The model results have been verified by comparing it with the numerical simulation data obtained from 3D device simulator Visual TCAD of Cogenda Int.

Ambipolarity reduction in DMG asymmetric vacuum dielectric Schottky Barrier GAA MOSFET to improve hot carrier reliability

An explicit surface potential and subthreshold current model for novel Dual Metal Gate (DMG) Asymmetric Vacuum (AV) as gate dielectric Schottky Barrier (SB) Cylindrical Gate All Around (CGAA) MOSFET with the incorporation of localized charges (Nf) is developed to provide excellent immunity against threshold voltage (Vth) degradation due to hot carriers. Hot carrier induced Localized Charges (LC) either positive or negative leads to degrade the threshold of the device. The major advantage of the proposed DMG-AV-SB-CGAA MOSFET is that it mitigates the ambipolar behavior thus offering very good on current to off current ratio; and also reduces the electron temperature which leads to less hot carrier generation thus lesser degradation in Vth and improved Hot Carrier reliability.The surface potential is determined for three different regions by solving 1-D Poisson’s and 2-D Laplace equation through separation of variable method to facilitate an optimal model for calculating the subthreshold drain current from Si-SiO2 interface boundary. The developed model results are in good agreement with that of ATLAS-TCAD simulation.

Analytical Subthreshold Current and Subthreshold Swing Models for a Fully Depleted (FD) Recessed-Source/Drain (Re-S/D) SOI MOSFET with Back-Gate Control

Two-dimensional (2D) analytical models for the subthreshold current and␣subthreshold swing of the back-gated fully depleted recessed-source/drain (Re-S/D) silicon-on-insulator (SOI) metal–oxide–semiconductor field-effect transistor (MOSFET) are presented. The surface potential is determined by solving the 2D Poisson equation in both channel and buried-oxide (BOX) regions, considering suitable␣boundary conditions. To derive closed-form expressions for the subthreshold characteristics, the virtual cathode potential expression has been derived in terms of the minimum of the front and back surface potentials. The effect of various device parameters such as gate oxide and Si film thicknesses, thickness of source/drain penetration into BOX, applied back-gate bias voltage, etc. on the subthreshold current and subthreshold swing has been analyzed. The validity of the proposed models is established using the Silvaco ATLAS™ 2D device simulator.

Analytical subthreshold current modeling of nanoscale ultra-thin body ultra-thin box SOI MOSFETs with a vertical gaussian doping profile

Based on the evanescent-mode analysis, an insightful study of the channel potential is performed for the nanoscale ultra-thin body ultra-thin box SOI MOSFETs with a vertical Gaussian doping. And a two-dimensional (2D) analytical subthreshold current model is presented. The front and the back channel subthreshold currents are effectively derived using the inversion layer current density model which takes the Gaussian doping into account. The accuracy of the model has been verified by 2D numerical device simulations using Sentaurus Technology Computer-Aided Design (TCAD) from Synopsys. The model provides a deep understanding and can be instrumental for the nanoscale ultra-thin body ultra-thin box SOI MOSFETs with a non-uniform doping profile operating in the subthreshold regime.