Subthreshold Current Research Articles

Heterozygous expression of a Kcnt1 gain-of-function variant has differential effects on somatostatin- and parvalbumin-expressing cortical GABAergic neurons

More than 20 recurrent missense gain-of-function (GOF) mutations have been identified in the sodium-activated potassium (KNa) channel gene KCNT1 in patients with severe developmental and epileptic encephalopathies (DEEs), most of which are resistant to current therapies. Defining the neuron types most vulnerable to KCNT1 GOF will advance our understanding of disease mechanisms and provide refined targets for precision therapy efforts. Here, we assessed the effects of heterozygous expression of a Kcnt1 GOF variant (Kcnt1Y777H) on KNa currents and neuronal physiology among cortical glutamatergic and GABAergic neurons in mice, including those expressing vasoactive intestinal polypeptide (VIP), somatostatin (SST), and parvalbumin (PV), to identify and model the pathogenic mechanisms of autosomal dominant KCNT1 GOF variants in DEEs. Although the Kcnt1Y777H variant had no effects on glutamatergic or VIP neuron function, it increased subthreshold KNa currents in both SST and PV neurons but with opposite effects on neuronal output; SST neurons became hypoexcitable with a higher rheobase current and lower action potential (AP) firing frequency, whereas PV neurons became hyperexcitable with a lower rheobase current and higher AP firing frequency. Further neurophysiological and computational modeling experiments showed that the differential effects of the Kcnt1Y777H variant on SST and PV neurons are not likely due to inherent differences in these neuron types, but to an increased persistent sodium current in PV, but not SST, neurons. The Kcnt1Y777H variant also increased excitatory input onto, and chemical and electrical synaptic connectivity between, SST neurons. Together, these data suggest differential pathogenic mechanisms, both direct and compensatory, contribute to disease phenotypes, and provide a salient example of how a pathogenic ion channel variant can cause opposite functional effects in closely related neuron subtypes due to interactions with other ionic conductances.

Heterozygous expression of a Kcnt1 gain-of-function variant has differential effects on somatostatin- and parvalbumin-expressing cortical GABAergic neurons.

More than 20 recurrent missense gain-of-function (GOF) mutations have been identified in the sodium-activated potassium (KNa) channel gene KCNT1 in patients with severe developmental and epileptic encephalopathies (DEEs), most of which are resistant to current therapies. Defining the neuron types most vulnerable to KCNT1 GOF will advance our understanding of disease mechanisms and provide refined targets for precision therapy efforts. Here, we assessed the effects of heterozygous expression of a Kcnt1 GOF variant (Kcnt1Y777H) on KNa currents and neuronal physiology among cortical glutamatergic and GABAergic neurons in mice, including those expressing vasoactive intestinal polypeptide (VIP), somatostatin (SST), and parvalbumin (PV), to identify and model the pathogenic mechanisms of autosomal dominant KCNT1 GOF variants in DEEs. Although the Kcnt1Y777H variant had no effects on glutamatergic or VIP neuron function, it increased subthreshold KNa currents in both SST and PV neurons but with opposite effects on neuronal output; SST neurons became hypoexcitable with a higher rheobase current and lower action potential (AP) firing frequency, whereas PV neurons became hyperexcitable with a lower rheobase current and higher AP firing frequency. Further neurophysiological and computational modeling experiments showed that the differential effects of the Kcnt1Y777H variant on SST and PV neurons are not likely due to inherent differences in these neuron types, but to an increased persistent sodium current in PV, but not SST, neurons. The Kcnt1Y777H variant also increased excitatory input onto, and chemical and electrical synaptic connectivity between, SST neurons. Together, these data suggest differential pathogenic mechanisms, both direct and compensatory, contribute to disease phenotypes, and provide a salient example of how a pathogenic ion channel variant can cause opposite functional effects in closely related neuron subtypes due to interactions with other ionic conductances.

An 11 nW, ＋0.34 °C/−0.38 °C inaccuracy self-biased CMOS temperature sensor at sub-thermal drain voltage

This paper presents a low-power, high-accuracy self-biased full CMOS temperature sensor based on sub-threshold currents at sub-thermal drain voltage. The sensor achieves high accuracy and minimal corner dependence by generating sub-threshold current ratios using NMOS transistors of different sizes operating at sub-thermal drain voltage. The proposed self-biased all-CMOS temperature sensing architecture enhances sensitivity by up to seven times and improves linearity. The overall stability under temperature fluctuations is significantly enhanced by utilizing a substrate diode structure that maintains constant current variation. Additionally, a high-threshold comparator with a fast response compresses the oscillator reset voltage difference, enabling ultra-low power operation. Timing logic control is employed to discard unstable cycle outputs, thereby reducing errors and achieving high-accuracy outputs. Operating at 1 V, the circuit consumes only 11 nW at 27 °C in a 180 nm CMOS process. It achieves a peak-to-peak inaccuracy of ＋0.34 °C/−0.38 °C from −10 to 100 °C after two-point calibration, with a resolution of 40 mK and a resolution FoM as low as 3.7 pJK2.

Design and investigation of electrostatic doped heterostructure vertical Si(1-x)Gex/Si nanotube TFET

Researchers are inclining toward heterostructures suitable lattice matching, in Tunnel FETs to eliminate the difficulties of decreased On-Current, subthreshold swings, and ambipolar behavior. Nowadays, Electrostatic doping (ED) is a scrutinized substitute device for creating areas with a high electron or hole density to the conventional doped devices. This manuscript proposes an Electrostatic Doped Heterostructure Vertical Si(1-x)Gex/Si Nanotube Tunnel Field Effect with performance scanned by analyzing the different device parameters, considering the energy band diagram, concentrations of electrons, holes, potential, and electric field. In comparison to the Nanowire TFETs, the area, and rate of tunneling of the proposed device stand superior with a better ION/IOFF ratio of 1.56∗1013 and a lower OFF-current of about ∼10−18A/μm. The device exhibits a Drain current (IDS) of 2.39∗105A/μm. The architecture of the suggested device possessing Si(1-x)Gex/Si structure exhibits enhanced characteristics like improved steepness of the sub-threshold slope, ION/IOFF ratio, drain current, and lowered OFF-current.

A novel ballistic model for the subthreshold behavior of nanosheet transistors

A novel ballistic model for the subthreshold current of nanosheet transistors is successfully developed based on the Landauer approach with the three-dimensional number of channels. The ballistic threshold voltage can also be achieved through the calculated free charge density induced by the three-dimensional density-of-states equal to the substrate doping concentration. It indicates that under the low drain voltage corresponding to the Fermi distribution function, the subthreshold current is mainly governed by the low contact potential. However, under the high drain voltage corresponding to the Fermi distribution function, the thermal voltage, instead of the contact potential between the source and drain, initiates the subthreshold current. Besides subthreshold current and threshold voltage, the ballistic conductance and subthreshold swing are also revealed in the subthreshold conduction. It indicates that the thin silicon, thin gate oxide, heavy substrate doping density, and high work function will alleviate the ballistic effects, decrease the subthreshold current/swing, and increase the threshold voltage/ballistic resistance.

Analytical modeling of drain current for DG-Graphene Nanoribbon Vertical Tunnel FET

The semi-classical current transport model is used in this study to examine the drain current model for Double-Gate (DG) Dual-Material-Gate (DMG) Graphene-Nanoribbon (GNR) Vertical TFETs. It takes into account the contact potential (VGS, VDG), the impact of the oxide thickness (tOX), and the carrier mobility (μ). The device’s channel length is 50 nm, and the energy bandgap is 0.26 eV when the GNR ribbon width is 10 nm. The bandgap varies with the GNR ribbon width. The data from the simulation of TCAD tools are compared to an analytical result of the drain current. The current transport model shows good agreement. It is clear that a GNR with a 5 nm width can switch ON and OFF at 0.5 V drain voltage, which shows low power bias operation. The suggested GNR-TFET is capable of producing an average subthreshold current of 16 mV/Dec, 1.74 × 10−4 A/μm on-state current, and 1.66 × 10−18 A/μm off-state current. The exceptional performance is made possible by the narrow bandgap, high mobility, and two-dimensional (2-D) nature of GNR.

Investigation of thermal stress effects on subthreshold conduction in nanoscale p-FinFET from Multiphysics perspective

The rising temperature due to a self-heating or thermal environment not only degrades the subthreshold performance but also intensifies thermal stress, posing a severe challenge to device performance and reliability design. The thermal stress effects on the ON-state performance of the p-type fin field-effect transistor were previously studied. However, as far as we know, how thermal stress affects its subthreshold conduction remains unclear, which is studied in this manuscript. The impact of thermal stress due to the self-heating of adjacent devices on subthreshold conduction is investigated by solving the quantum transport, thermal conduction, and force balance equations for ballistic transport and dissipative transport with phonon scattering. Then, the thermal stress effects at different ambient temperatures are further discussed and analyzed. The simulation results show that the OFF-state leakage current can be reduced by thermal stress, even up to 9.28% for the (110)/[001] device operating at an ambient temperature of 550 K, and its reduction is the comprehensive result of the thermal stress effects on the band structure, potential profile, carrier distribution, and source-to-drain tunneling. In addition, the thermal stress has no significant effects on subthreshold swing although it can change the magnitude of the subthreshold current. Moreover, the effect of thermal stress on subthreshold conduction is highly dependent on the thermal environment of the device and the crystal orientation of the channel semiconductor material.

Neural Field Dynamics: The Interplay of Local and Global Activity in Brain Function

Abstract: Recent advancements in neuroscience have spurred a paradigm shift away from strict localizationism towards an appreciation for the brain as a dynamic, interconnected network. This paper discusses the intricacies of neural field dynamics, emphasizing the role of local and global brain activities and their interplay in shaping cognitive processes and behaviors. We explore the concept of neural microfields and their collective influence at a distance, considering how even subthreshold electric currents generated by neural activity can modulate neuronal excitability and network states. The discussion extends to the brain's operation at the edge of criticality—a state theorized to optimize information processing and adaptability. We delve into how fluctuations in neural activity, potentially stemming from strong emotions or pathological states, can precipitate bifurcations in neuronal behavior, leading to various brain states or phase transitions. The implications of external electric fields, such as those used in neuromodulatory therapies, are also considered, highlighting their capacity to influence neuronal activity and alter systemic dynamics. This review integrates perspectives from computational neuroscience, dynamical systems theory, and electrophysiology to construct a holistic understanding of neural field dynamics and their significance in the functioning of the brain. The paper aims to theoretically contribute to the ongoing dialogue in neuroscience regarding the non-linear and emergent properties of neural networks, paving the way for future research and clinical innovations.

An analytical subthreshold I–V model of SiC MOSFETs

In this article, an analytical I–V model for calculating subthreshold current of SiC MOSFETs is presented. This model starts with planar MOSFETs and utilizes the one-dimensional Poisson’s equation to derive an analytical expression for the surface potential. Subsequently, it employs this expression as a foundation for subthreshold current calculations. Then the model is extended to DMOSFETs based on the fact that channel current formation mechanism of DMOSFETs is similar to that of planar MOSFETs. Comparative analysis of our model calculations with two-dimensional numerical simulation software reveals that our model exhibits a high degree of agreement in the case of planar MOSFETs and DMOSFETs. Interface traps were also considered in our analytical model, which agrees well with experimental data published elsewhere. Furthermore, the model retains a certain degree of accuracy and predictive capability even in the presence of short-channel effect. Our subthreshold model becomes complementary to existing models which only describe the I–V characteristics of SiC MOSFETs when the transistors operate above the threshold voltages.

Modeling and Simulation Characteristics of a Highly-Sensitive Stack-Engineered Junctionless Accumulation Nanowire FET for PH3 Gas Detector

In this manuscript, a Stack Engineered Junctionless Accumulation Nanowire FET (SE-JAM-NW FET) has been proposed for low - power and high sensitivity phosphine (PH3) gas detection applications. In comparison to a standard nanowire FET, the SE-JAM-NW FET is used at nanoscale dimensions because of its inherent benefits, including low cost, improved portability, low Off- state current and increased On-state current with low - power consumption. To implement the SE-JAM-NW FET as a phosphine gas sensor, four catalytic metals, Platinum (Pt), Rhodium (Rh), Iridium (Ir) & Palladium (Pd) have been employed as gate electrodes. For designing gas sensor, various electric parameters like potential, electron concentration, recombination rate and electron velocity are evaluated for PH3 gas detection. To forecast the sensor’s response, analog characteristics like changes in drain current, transconductance & output conductance are being simulated for different catalytic metal work functions (200 meV, 150 meV, 100 meV and 50 meV) at the gate electrode. The variation in On-state current-to-Off-state current ratio (IOn/IOff), On-state current (IOn) & subthreshold leakage current (IOff) for sensing the gas molecules has been used to quantify the sensitivity. The effects of silicon pillar-based radius variation and channel length variation on the sensitivity-based parameters are also investigated. Each catalytic metal exhibits improved sensitivity with increased channel length and decreased radius. The outcomes of the ATLAS 3-D device simulator’s numerical simulation closely match with those of the derived analytical model.

Modeling of negative capacitance underlap graded-channel junction accumulation mode junctionless FET in nano-scale regime

Analytical modeling of negative capacitance (NC) graded-channel (GC) underlap junction accumulation mode (JAM) JL-FET is presented in this literature. Here, the surface potential, threshold voltage, sub-threshold drain current, sub-threshold swing (SS) and DIBL are obtained by solving the 2D Poisson's equation and Landau-Khalatnikov (LK) equation simultaneously. Performances of the proposed NC-GC-JAM-JL-FET is analyzed in detail for the variations in FE-layer thickness, gate-length, underlap length, graded channel ratio and Si-film thickness. The proposed model is calibrated with the experimental data to establish its acceptability. The proposed device is also simulated in the Silvaco ATLAS device simulator, which shows very good agreement with the analytical model. The present paper establishes the remarkable prospect of the proposed architecture to be operated for low-power application in nano-scale regime.

A ballistic model for subthreshold current and threshold voltage of the dual-material-gate nanosheet MOSFET

— A ballistic model for subthreshold current of the dual-material-gate (DMG) nanosheet (NS) MOSFET is developed based on the Landauer approach, three-dimensional scaling equation, and the continuity of subthreshold current at the interface between the control gate and screen gate in the channel, The work function difference between the screen gate and control gate can be converted into the new interface-quasi-fermi-potential (IQFP) at the junction between different gate regions. Through the IQFP, the ballistic subthreshold current for DMG NS MOSFET is successfully developed. With the determined subthreshold current, the ballistic threshold voltage can also be achieved by the constant current method. Under the low and high drain voltage corresponding to their IQFPs, the subthreshold behavior is mainly governed by the contact potential and thermal voltage, respectively. Furthermore, Ohm's law regarding ballistic resistance for the DMG NS MOSFET can still be valid in the subthreshold conduction.

Analytical modeling of recessed double gate junctionless field‐effect‐transistor in subthreshold region

AbstractIn this work, we have presented an analytical model for a recently proposed symmetrical recessed double gate junctionless field‐effect transistor (R_DGJLFET) operating in subthreshold region. The model has been developed by solving a two‐dimensional Poisson's equation in three continuous rectangular silicon regions, resulting in explicit expressions for surface potential, center potential, and eventually the subthreshold drain current. The model provides deeper physical insights by successfully incorporating the effect of various design parameters such as doping concentration, gate length, gate work function, and effective oxide thickness on the subthreshold drain current. Moreover, the effect of variations in gate length on the subthreshold slope has also been presented. The model results have been validated with the simulation results obtained from the Silvaco Atlas tool and found reasonably close.

Assessment of the Biosensing Capabilities of SiGe Heterojunction Negative Capacitance-Vertical Tunnel Field-Effect Transistor.

In this study, a comparison of the negative capacitance vertical tunnel field-effect transistor (NC-VTFET) and VTFET for biosensing applications was conducted. Dielectrically modulated TFET demonstrates better sensitivity than the traditional metal oxide field effect transistor as a biosensor in label-free biosensing applications. The TFET biosensor, however, has much room for advancement by enhancing its DC characteristics. This research addresses the impact of ferroelectric gate oxide for integration of negative capacitance (NC) effect with the SiGe heterojunction pocket at the source-channel junction to enhance performance for biosensor applications. By putting the NC layer over SiO2, the channel voltage increases with decreased subthreshold slope and OFF current, thereby creating an NC effect. Because SiGe has a narrow band gap, pocket doping of SiGe near the source channel junction will increase the concentration of charge carriers, improving the band-to-band tunneling. In order to aid in the integration of biomolecules and to modulate band-to-band tunneling based on charge density (qf), dielectric constant (k), temperature, and cavity length, a cavity is additionally inserted above the source channel junction and underneath the NC layer, near to SiO2. These values were compared with and without the incorporation of NC layer with respect to various electrical properties such as drain current (Id), sensitivity, and electric field (E). According to the findings, labeled and label-free biosensors' sensitivity may be increased by incorporating the NC effect into VTFET biosensors.

Analytical Modeling of Cryogenic Subthreshold Currents in 22-nm FDSOI Technology

Analytical Modeling of Cryogenic Subthreshold Currents in 22-nm FDSOI Technology

Source of IC power consumption and low power design

In these years, with the continuous development of 14nm and 7nm chip processes and the increasing popularity of computers, cell phones, and smart homes, the growing market of electronic products and ultra-fine research for the reliability of the chip requirements gradually increased. The method of reducing power consumption in the new context of new technology is called the chip field die-cut concern. This paper mainly summarizes two aspects of power consumption sources and methods to reduce power consumption, to provide a reference basis for future research directions: First, the major sources of power consumption are static power consumption and dynamic power consumption. The primary sources of static power consumption are sub-threshold leakage and gate leakage current. This paper also mentions some other leakage currents, such as reverse bias PN junction current and induced leakage current, which can be more carefully considered when exploring methods to reduce power consumption. A more comprehensive consideration when exploring ways to reduce power consumption. Dynamic power consumption is mainly divided into Switching power and Internal power and short-circuit power. Then we summarize the existing methods which can reduce power consumption: Clock gating (including Clock gating without a latch and Clock gating with a latch), Dynamic voltage and frequency scaling, multi-supply and multi-voltage technology, Power gating and multi-threshold voltage. These methods are from a proprietary perspective to reduce power consumption.

Numerical Simulation of Hetero Dielectric Trench Gate JAM Gate-All-Around FET (HDTG-JAM-GAAFET) for Label Free Biosensing Applications

The label free detection of various biomolecules associated with different diseases has been proposed in this manuscript using a novel biosensor design named as the Hetero Dielectric Trench Gate Junctionless Accumulation Mode Gate-All-Around FET (HDTG-JAM-GAAFET). This biosensor employs a silicon cylindrical Gate All Around FET which operates in Junctionless Accumulation Mode (JAM) and has a hetero dielectric layer comprised of SiO2 and HfO2. The cylindrical gate structure’s metal gate is trenched into the Hafnium oxide dielectric layer, which provides the gate with enhanced control over the surface characteristics of the channel. A Trench Gate architecture in a hetero dielectric Gate All Around FET is emulated for the biosensing for the first time. The HDTG-JAM-GAAFET has been compared to Normal Gate JAM Gate-All-Around FET (NG-JAM-GAAFET) biosensors immobilizing a variety of neutral biomolecules and biomolecules having a range of positive and negative charges. The effect of biomolecules on HDTG-JAM-GAAFET biosensor’s output properties, including surface potential, electron concentration, threshold voltage drift (ΔVTH), subthreshold leakage current (IOFF), subthreshold slope (SS), switching ratio (ION/IOFF), ION current sensitivity, transconductance (gm), output conductance (gd), channel resistance (Rch) and intrinsic gain ( AVint ) has been studied. For instance, HDTG-JAM-GAAFET biosensor has drain ON-current sensitivity (SION) which is 67.68% greater for gelatin biomolecules, 69.4% higher for positive biomolecules, and 8% higher for negative biomolecules bound in the nanogap cavity than that of a Normal Gate JAM Gate-All-Around FET. The proposed device exhibits exceptional performance characteristics and it can effectively identify specific biomolecules to diagnose many diseases, such as breast cancer, lung cancer, and numerous viral infections, using their respective biomarkers.

Low-Leakage Double-Body MOSFET: A Promising Circuit-Level Technique for Deep-Submicron Analog Integrated Circuit Design

Since the leakage currents are dramatically increasing while the MOS transistors scale down to deep-submicron processes, the [Formula: see text]–[Formula: see text] characteristic of the channel is varied unintentionally. As a result, the analog integrated circuit (IC) designs based on it (at above 100-nm technologies) will malfunction. In this paper, a novel low-leakage double-body MOSFET (LLDB-M), as a circuit-level scheme in answering to the need for the current-mode analog IC design in deep-submicron processes, is proposed. In this technique, the sub-threshold and gate-oxide tunneling leakage currents (as two major parts) are reduced via lowering the gate-source voltage and increasing the threshold voltage of the MOS transistor. An LLDB-M consists of two typical transistors — the first one is the main transistor and the latter implements the shift-voltage to reduce the gate-source voltage and floor of the channel leakage currents. The drain, gate, and body of the main transistor as well as the body and source of the second one, organize the terminals of an LLDB-M. The proposed LLDB-M transistors are replaced with large-leakage transistors in a translinear loop in the weak inversion region and then the commonly-used circuits such-as the current mirror, one-quadrant multiplier-divider (at both up-down and stack topologies), the true RMS-DC converter, and the log-domain low-pass-filter are designed. The effectiveness and performance of the proposed LLDB-M technique and circuits are evaluated using HSPICE software in 22-nm BSIM4 CMOS process and Cadence Virtuoso tool in 65-nm TSMC CMOS technology. Post-layout simulation results show that the proposed circuit-level method by considerably reducing leakage currents could ensure the effective function of the current-mode analog IC designs in deep-submicron technologies. Also, comprehensive simulations have been performed to prove the robustness and reliability of the proposed circuits against process, voltage and temperature (PVT) changes.

Mobile ions entering the IGBT gate oxide - electrical detection and failure localization by lock-in thermography

Small mobile ions, especially sodium and potassium are known to have the ability to infiltrate and move within gate oxide layers of silicon MOS devices. The ion transport in silicon oxide is either a temperature-driven, isotropic diffusion process, or an electrical ion current in presence of an electric field. Therefore, the high temperature gate bias test with negative polarity provides ideal conditions to identify the presence of mobile ions in the gate oxide of IGBT and MOSFET. Mobile ions in sufficient concentration can severely affect the electric characteristics, such as the turn-on and turn-off behavior of the MOS channel, by creating a shift in the gate threshold voltage or excessive sub-threshold currents. This paper shows several examples of how mobile ions can get into the gate oxide, e.g., via cracks in top side metallization, or by corrosive attack of cap layers. All these different failure modes develop the same electrical failure signature after temperature and/or gate bias stress. During the investigations on mobile ions, a special lock-in thermography method was developed that allows to localize the defect sites in the semiconductor by taking advantage of exclusive excitation of MOS cells affected by mobile ion contamination. Finally, after defect localization, further analytical methods can be applied to identify the exact nature of the access path to the gate oxide. Based on the test and analytical routine described above, a special test method was developed that allows to evaluate the permeability of the semiconductor chip top side structures towards mobile ions and to check for weak spots and potential leakage paths.

Studying the Performance of Underlap GAA-FET

Abstract: This paper investigates the performance of underlap Gate-All-Around Field Effect Transistor (GAA FET) of 22nm gate length and evaluates the short channel performance of the device. Underlap GAA FET structure can be utilized to increase the drive current of the nanowire devices. In this work, underlap rectangular GAA FET is designed by extension of underlap regions on source/drain of GAA FET to increase the performance. This underlap device is increasing the capacitances by adding the fringing capacitances to parasitic capacitances which increases the fringing field from gate electrode to underlap regions. In this also investigating the electrical parameters on various performance metrics like threshold voltage (Vth), ON current (ION), OFF current or subthreshold leakage current (IOFF), ON-OFF current ratio (ION/IOFF) and short channel effects such as Subthreshold slope (SS) and DIBL (Drain Induced Barrier Lowering) of underlap GAA FET are systematically evaluated and analysed. In the present study, GAA FET and underlap GAA FET device performances are investigated through ATLAS device simulator from Silvaco.