Modeling of negative capacitance underlap graded-channel junction accumulation mode junctionless FET in nano-scale regime

Abstract

Analytical modeling of negative capacitance (NC) graded-channel (GC) underlap junction accumulation mode (JAM) JL-FET is presented in this literature. Here, the surface potential, threshold voltage, sub-threshold drain current, sub-threshold swing (SS) and DIBL are obtained by solving the 2D Poisson's equation and Landau-Khalatnikov (LK) equation simultaneously. Performances of the proposed NC-GC-JAM-JL-FET is analyzed in detail for the variations in FE-layer thickness, gate-length, underlap length, graded channel ratio and Si-film thickness. The proposed model is calibrated with the experimental data to establish its acceptability. The proposed device is also simulated in the Silvaco ATLAS device simulator, which shows very good agreement with the analytical model. The present paper establishes the remarkable prospect of the proposed architecture to be operated for low-power application in nano-scale regime.