Submicron Channel Research Articles

Nano-rheology printing of sub-0.2 μm channel length oxide thin-film transistors

Down-scaling of the channel length of a fully solution-processed oxide thin-film transistor (TFT) to the nanometer-scale is the key to accessing next-generation devices for Internet-of-Things technology. In this work, we report on the fabrication of an oxide TFT with a channel length of 160 nm, which is far less than those obtained by the current direct-printing techniques, by a newly developed nano-rheology printing (nRP) method. The device had an on/off current ratio, subthreshold voltage, hysteresis, and field-effect mobility of approximately 107, 1.7 V, 0 V, and 0.16 cm2 Vs−1, respectively. The key to achieving the sub-micron channel printed TFT is the introduction of a new amorphous La–Ru–O material, which exhibits relatively good conductivity and excellent nRP properties at the nanoscale, for source/drain electrode patterns. Such a short-channel TFT would never be achieved with conventional printing methods, and hence, this approach is highly important for accessing next-generation low-cost, large-area and environmentally friendly printed electronics.

Vacuum field-effect transistor with a deep submicron channel fabricated by electro-forming

Vacuum field-effect transistors (VFETs) with channel lengths down to 500nm (i.e., the deep submicron scale) were fabricated with the mature technology of the surface conduction electron emitter fabrication process in our former experiments. The vacuum channel of this new VFET was generated by using the electro-forming process. During electro-forming, the joule heat cracks the conductive film and then generates the submicron scale gap that serves as the vacuum channel. The gap separates the conductive film into two plane-to-plane electrodes, which serve as a source (cathode) electrode and a drain (anode) electrode of the VFET, respectively. Experimental results reveal that the fabricated device demonstrates a clear triode behavior of the gate modulation. Fowler-Nordheim theory was used to analyze the electron emission mechanism and operating principle of the device.

Top-Contact Self-Aligned Printing for High-Performance Carbon Nanotube Thin-Film Transistors with Sub-Micron Channel Length.

Semiconducting single-wall carbon nanotubes are ideal semiconductors for printed thin-film transistors due to their excellent electrical performance and intrinsic printability with solution-based deposition. However, limited by resolution and registration accuracy of current printing techniques, previously reported fully printed nanotube transistors had rather long channel lengths (>20 μm) and consequently low current-drive capabilities (<0.2 μA/μm). Here we report fully inkjet printed nanotube transistors with dramatically enhanced on-state current density of ∼4.5 μA/μm by downscaling the devices to a sub-micron channel length with top-contact self-aligned printing and employing high-capacitance ion gel as the gate dielectric. Also, the printed transistors exhibited a high on/off ratio of ∼105, low-voltage operation, and good mobility of ∼15.03 cm2 V-1s-1. These advantageous features of our printed transistors are very promising for future high-definition printed displays and sensing systems, low-power consumer electronics, and large-scale integration of printed electronics.

Performance evaluation of channel length downscaling of various high voltage AlGaN/GaN power HEMTs

Channel length downscaling characteristics of various lateral AlGaN/GaN high electron mobility transistors (HEMTs) are simulated. Quasi‐constant‐field scaled MOS channel HEMTs show superior performance over two‐dimensional electron gas (2DEG) channel HEMTs at deep submicron channel lengths. The adverse effects of deep submicron channel length on threshold voltage, drain‐induced barrier lowering, subthreshold swing, transconductance and on‐off current ratio are seen to be much less pronounced in MOS channel HEMTs compared with 2DEG channel HEMTs. Switching capabilities of enhancement mode HEMTs at different channel lengths are evaluated and compared using a new intrinsic maximum switching frequency (fm,IG) figure‐of‐merit.

Design Considerations for ZnO Transistors Made Using Spatial ALD

We have used spatial atomic layer deposition (SALD) to fabricate metal oxide thin-film devices with unusually simple processes. Selective area deposition allows us to fabricate transistors and circuits additively and with digital design variations when used in combination with an inkjet-printed inhibitor. In a second approach, we use the conformal nature of SALD films to produce self-aligned sub-micron channel length vertical transistors that have large alignment tolerances and are suitable for high-performance thin-film electronics. We discuss device design considerations for both architectures.

Design Considerations for ZnO Transistors Made Using Spatial ALD

We have used spatial atomic layer deposition (SALD) to fabricate a variety of thin film transistors using zinc oxide as the semiconductor and aluminum oxide as the insulator. The conductive electrodes are formed either from aluminum-doped zinc oxide, or from thermally evaporated metals. Spatial ALD can be performed at atmospheric pressure, and can grow coatings very quickly. Deposition occurs without a requirement for valve timing, by moving the substrate relative to the precursors flowing from a coating head. The proximity of the substrate to the coating head is controlled via a gas bearing design – allowing SALD to operate with purge times that are equivalent to the precursor exposure times (sub-second) unlike traditional chamber-based systems. In this talk we will discuss examples of thin film electronics with architectures that are enabled by ALD, with a particular focus on spatial ALD. We use the well known conformality of ALD to build self-aligned, sub-micron channel length, vertical transistors. The vertical transistor electrical performance is impressive compared to amorphous silicon TFTs, for example, yet the alignment tolerances inherent in the fabrication process are large.Our second approach to fabricating devices uses selective area deposition, with inkjet-printed inhibitor, to pattern all the active layers. We build full transistors and circuits using one inhibitor ink, the SALD system, and an oxygen plasma to clean the substrate. Performance of the resulting transistors and circuits match photolithographically patterned ones.

Submicron organic thin-film transistors fabricated by film profile engineering method

In this work, we explore and demonstrate the feasibility of a film profile engineering (FPE) concept in fabricating pentacene-based organic thin-film transistors (OTFTs) with submicron channel length. The FPE scheme utilizes a suspended bridge built on the wafer and the specific deposition conditions to form thin films with desirable profiles. In order to form a continuous pentacene channel under the bridge, the background pressure of thermal evaporator is adjusted by pumping down the filling N2 to a specific level. The results show that, by setting the deposition pressure at 3 mtorr, functional operations of OTFTs with channel length ranging from 0.4 to 0.6 μm are obtained.

Demonstration of tunable optical delay lines based on apodized grating waveguides

High-speed and tunable integrated optical delay lines are demonstrated based on silicon grating waveguides apodized by the super-Gaussian function. The submicron channel waveguides with inward-apodized gratings are fabricated by deep-ultraviolet optical lithography. Characterization of the compact delay lines shows that they offer true-time delays as long as 132 ps, tuning range of ~86 ps, and a minimum bit rate of ~13 Gb/s. For lower bit rates, delays as high as 220 ps and tuning range of 174 ps are feasible.

Fabrication of a SiC Double Gate Vertical Channel JFET and It's Application in Power Electronics

The fabrication process of an innovative epitaxial trench JFET with vertical channel and double gate control is reviewed. Due to the excellent doping and thickness control of the epitaxial re-growth techniques, the sub-micron channel can be tailored for normally-on and -off operation. Due to the vertical channel design the epitaxial trench JFETs have narrow cell pitch for high-density power integration and high saturation current capabilities. The excellent performance of these fabricated and packaged JFET devices is demonstrated with on-wafer measurements and power switching tests. High current conduction tests are performed at room temperature and elevated temperatures of 125{degree sign}C with switching frequencies of 30 kHz and 200 kHz.

Submicron optical waveguides and microring resonators fabricated by selective oxidation of tantalum

Submicron tantalum pentoxide ridge and channel optical waveguides and microring resonators are demonstrated on silicon substrates by selective oxidation of the refractory metal, tantalum. The novel method eliminates the surface roughness problem normally introduced during dry etching of waveguide sidewalls and also simplifies fabrication of directional couplers. It is shown that the measured propagation loss is independent of the waveguide structure and thereby limited by the material loss of tantalum pentoxide in waveguides core regions. The achieved microring resonators have cross-sectional dimensions of ~600 nm × ~500 nm, diameters as small as 80 µm with a quality, Q, factor of 4.5 × 10(4), and a finesse of 120.

Nanoimprint assisted inkjet printing to fabricate sub-micron channel organic field effect transistors

Solution processed poly(3-hexylthiophene) organic field effect transistors with channel lengths down to 750nm were fabricated by nanoimprint assisted inkjet printing. The nanoimprint lithography was used to define sub-micron channels into a resist because of its high resolution. A silver-containing ink was inkjet-printed onto a pre-patterned resist layer to form a metallic film, which acts as source and drain electrodes after lift-off. This process replaces the expensive vacuum evaporation of gold electrodes. The transistor short channel effect was suppressed successfully by constant field downscaling. However, samples with inkjet-printed silver electrodes have limited current density. They also have lower effective charge mobility due to higher charge injection barrier, as well as the rough metal surface. Gold nanoparticles were added into the silver ink to modify its work function and therefore reduce the contact resistance between electrodes and polymer. This emphasizes the importance of the metal-semiconductor contact especially for short channel organic transistors.

Submicron Channel Fabrication in Photoresist Film Using Continuous Wave Laser

Laser fabrication of submicron hollow channel using a continuous wave (CW) light source is investigated. In conventional laser fabrication, CW laser beam affects the immediate vicinity of a beam exposure area because the fabrication employs a heat mode process. Our method proposed, however, three-dimensionally localizes the exposure area in a focal plane by controlling the reaction time constant of a photoresist film. As a result, we have fabricated a submicron hollow channel in the photoresist film using the CW laser source.

Nanoimprinted Step-Edge Vertical-Channel Organic Transistors

Flexible and low-cost organic field-effect transistors (OFETs) are desired for a variety of organic electronics. In this paper, we describe step-edge vertical-channel OFETs (SVC-OFETs) having excellent device performance fabricated by nanoimprint lithography and a self-aligned process. SVC-OFETs can be used to fabricate a submicron channel by forming the channel region around the step edge. The carriers flow in the vertical direction in the short channel along the step-edge structure. Both n- and p-channel FETs are also realized by a solution process.

Nanoimprinted Step-Edge Vertical-Channel Organic Transistors

Flexible and low-cost organic field-effect transistors (OFETs) are desired for a variety of organic electronics. In this paper, we describe step-edge vertical-channel OFETs (SVC-OFETs) having excellent device performance fabricated by nanoimprint lithography and a self-aligned process. SVC-OFETs can be used to fabricate a submicron channel by forming the channel region around the step edge. The carriers flow in the vertical direction in the short channel along the step-edge structure. Both n- and p-channel FETs are also realized by a solution process.

Low-noise submicron channel graphene nanoribbons

We present a graphene nanoribbon fabrication method based on a nanowire mask. Using a four-probe setup, single-layer nanoribbon (SLR) and bilayer nanoribbon (BLR) show low-frequency noise levels lower than (comparable to) the SLRs (BLRs) achieved by hydrogen-silsesquioxane based methods. Submicron channel SLR and BLR both show conductance quantization at 77 K, which suggests that quasi-one-dimensional quantum transport can be achieved. The conductance plateaus in BLR are less pronounced than those in SLR.

Self-organization of linear nanochannel networks

A theoretical study has been conducted to explore the mechanics of self-organizing channel networks with dimensions in the submicron range and nanorange. The channels form by the partial release and bond back of prestressed thin films. In the release phase, the film spontaneously buckles into wrinkles of a certain wavelength, followed by a bond-back phase in which the final channel geometry is established through cohesive interface attractions. Results are presented in terms of the channel spacing, height, and width as a function of the film stiffness, thickness, eigenstrain, etch width, and interface energy. We have identified two dimensionless parameters that fully quantify the network assembly, showing excellent agreement with experiments. Our results provide valuable insight for the design of submicron and nanoscale channel networks with specific geometries.

High-Speed Operation of Step-Edge Vertical-Channel Organic Transistors with Pentacene and 6,13-Bis(triisopropyl-silylethynyl) Pentacene

Organic field-effect transistors (OFETs) with a novel structure, step-edge vertical-channel OFETs (SVC-OFETs), have been developed to obtain a short channel by a self-aligned process. SVC-OFETs enable the fabrication of a submicron channel by forming the channel region around the step-edge structure. Carriers flow in the vertical direction in the short channel of the step-edge structure. SVC-OFETs show excellent device performance characteristics with a high current and a high cutoff frequency of approximately 1.5 MHz, which is a very high value for organic transistors.

Broadening of neutral solute band in electroosmotic flow through submicron channel with longitudinal non-uniformity of zeta potential

The present study is concerned with broadening of neutral solute band in electrically driven flow through a straight channel with longitudinally varying zeta potential. The present analysis takes into account effects that are important for submicron channels, namely, variation of the excess conductivity in the diffuse part of the electric Double Layer and the non-uniformity of the velocity profile within the Double Layer. Initially, the combined, electroosmotic and pressure driven flow through a straight channel is addressed for the case of longitudinal variation of zeta potential. Using the obtained distribution of the hydrodynamic velocity, the plate height for a non-electrolyte neutral solute is interrelated with the longitudinal distribution of the electrokinetic potential. Several examples of cross-section geometry and electrolyte composition are discussed.

Submicron Trenches Reduce the Pseudomonas fluorescens Colonization Rate on Solid Surfaces

Bacterial adhesion and spreading on biomaterials are considered key features of pathogenicity. Roughness and topography of the substrate have been reported to affect bacterial adhesion, but little is known about their effect on spreading. Submicron row and channel tuning with bacterial diameter (S2) were designed to test bacterial motility on these surfaces. Random nanometer-sized structures (S1) were used as controls. Optical microscopy and AFM were employed to detect biological and surface pattern details in the micro- and nanoscale, respectively. Results showed that motility strategies (flagella orientation, elongation, aggregation in rafts, formation of network structures, and development of a bacterial frontier) were affected by the presence of submicropatterns. Importantly, the rate of bacterial spreading on S2 was significantly reduced and influenced by the orientation of the submicropatterns. Consequently, submicroengineered substrates could be employed as a tool to downgrade bacterial colonization. Such patterns could impact on the design of proper engineered structures to control biofilm spreading on solid surfaces.

Organic thin film transistors and polymer light-emitting diodes patterned by polymer inking and stamping

To fully realize the advantages of organic flexible electronics, patterning is very important. In this paper we show that a purely additive patterning technique, termed polymer inking and stamping, can be used to pattern conductive polymer PEDOT and fabricate sub-micron channel length organic thin film transistors. In addition, we applied the technique to transfer a stack of metal/conjugated polymer in one step and fabricated working polymer light-emitting devices. Based on the polymer inking and stamping technique, a roll-to-roll printing for high throughput fabrication has been demonstrated. We investigated and explained the mechanism of this process based on the interfacial energy consideration and by using the finite element analysis. This technique can be further extended to transfer more complex stacked layer structures, which may benefit the research on patterning on flexible substrates.