Static Random Access Memory Cell Design Research Articles

Stable organic SRAM cell with p-type access transistors

This paper demonstrates the implementation of a static random access memory (SRAM) cell that is suitable for low-voltage organic thin-film transistors (OTFTs). SRAM is an essential component in electronic systems which can store data or instructions for various applications. We use p-type OTFTs for the access transistors to gain higher areal efficiency and better robustness than those of conventional OTFT-based SRAM construction. We verify the stability of the proposed SRAM cell and optimize the transistor sizes through SPICE simulation. Using test chip measurement, the correct write/read operation of the proposed SRAM cell is confirmed under a 10× imbalance of the on-current ratio. The proposed SRAM cell achieves a 50% area reduction and a 2.5× static noise margin improvement, compared to the existing OTFT SRAM cell design.

WITHDRAWN: Low power performance SRAM cell design

The Static Random Access Memory (SRAM) is shown vital in high performance portable VLSI Chips due to their performance and storage density. This paper presents the evaluating point by point recreation derive for the memory cells inform of the power, speed, and area investment funds acquired in the advanced cell configuration when contrasted with the standard regular architecture. The adiabatic low power technique is implements to enrich the configuration of 6T-SRAM cell. The approach and application of this adiabatic driver the more loss of energy dissipation to the ground (0 V) with ‘1’ to‘0’ transition is decreased to a larger degree in the memory cell. This method gives a lower degree of power reduction results compared with the standard adiabatic 6T-SRAM cell.

Design of a Bit-Interleaved Low Power 10T SRAM Cell with Enhanced Stability

The technology is shrinking in recent days which leads to growing concerns related to various design metrics. Leakage power tends to grow with the array size as most of the Static Random Access Memory (SRAM) cells operate in standby mode. The data to be written into the SRAM become difficult as the supply voltage decreases. So, stability in write mode requires enhancement. As SRAM is used for the on-chip computations, the faster write operation is required. The half-select issue in SRAM design needs to be eliminated so that bit interleaving architecture can be employed for the SRAM array enabling the protection from soft errors. A new Proposed 10 Transistor Bit-Interleaved SRAM cell has been designed addressing the above concerns. Employment of high-threshold voltage devices in read path and absence of NMOS device in one of the inverters reduces leakage power. Cut-off switch enables faster write operation and enhanced write stability. Cross point selection in write mode eliminates the half-select issue observed by carrying 1000 Monte-Carlo simulations. It has lower leakage power while holding 0 compared to 8 Transistor, Fully Differential 8 Transistor and Write Assist Low Power 11 Transistor SRAM cells at the worst fast-fast process corner for 0.9 V supply voltage. Write 1 Power Delay Product is lower than 8 Transistor, Fully Differential 8 Transistor and Write Assist Low Power 11 Transistor SRAM cells at slow-slow corner at 0.9V supply voltage. All the design metrics have been evaluated by performing post-layout simulation in Cadence Virtuoso in 45-nm technology.

Design and Analysis of SRAM cell using Body Bias Controller for Low Power Applications

Low power consumption of electronic devices has become one of the most desirable factors in the present day’s technology. Static random access memory (SRAM) being an integral part of most of the electronic gadget suffers from leakage current which results in static power dissipation and subsequently affects its performance particularly during standby or hold mode. This becomes crucial especially for those systems which are portable and have limited power supply. This work therefore proposes a body bias controller implemented with a 7T SRAM cell at 28 nm CMOS technology node which lowers the static power consumption and increases the hold static noise margin (HSNM) of SRAM during standby mode by changing the threshold voltage. Moreover, it also reduces write delay due to reduction in threshold voltage of proposed design without having a significant effect on write static noise margin and read static noise margin. It has been noticed that there is a reduction of 40%, 28%, 41.9% and 30% in static power dissipation whereas there is an enhancement of 19%, 14.2%, 6.6% and 5.2% in HSNM of the proposed design when compared to 6T SRAM cell, 7T SRAM cell, WRE8T SRAM cell and 9T SRAM cell, respectively. The proposed design can thus be a suitable alternative for low power SRAMs.

An ultra-low-power and high-performance SRAM cell design based on GNRFETs

ABSTRACT In this letter, we propose a new design of an ultra-low-power and high performance six – transistor (6 T) static random access memory (SRAM) cell using graphene nanoribbon field-effect transistors (GNRFETs). HSPICE (Simulation Program with Integrated Circuit Emphasis)-compatible compact GNRFETs model is used to design and validate the different SRAM cells. The proposed cell improves the performance in terms of power consumption, read data stability, and writeability at the low supply voltage. The proposed cell also significantly reduces the leakage power consumption due to excellent control on the gate leakage current. The small bandgap and the high ratio in a GNRFET device show great potential for high-speed nanoelectronics applications. The cell consumes ultra-low power due to its capability to operate below 0.5 V, which makes it suitable for low power applications.

Physics-Based Device-Circuit Cooptimization Scheme for 7-nm Technology Node SRAM Design and Beyond

This article presents a comprehensive assessment on the 6T static random access memory (SRAM) cell with 7-nm FinFET technology by implementing quantum physics-based device-circuit cooptimization. Seven key device design parameters and their multiple impacts on a 6T SRAM cell are systematically evaluated, focusing on materials band engineering, device design, circuit parameters tradeoff, and variation control. The area of SRAM cell under the same Fin quantization scheme remains constant in all evaluations. To the best of our knowledge, the most comprehensive discussion about circuit optimization from multiple device design parameters perspective is presented. Based on our cooptimization scheme, a SRAM cell is effectively designed. For a low-power and robust SRAM cell design, we achieve 56.7% reduction in leakage, 7.9% improvement in hold noise margin (HNM), 8.6% improvement in read noise margin (RNM), and 10.8% improvement in write margin (WM) at the expense of 19.3% increase in delay under design space of gate length (Lg) and spacer thickness (TSPC). For a high-speed SRAM cell design, we recommend focusing on the optimization of architecture and peripheral circuits. This framework not only has the advantages of easy implementation, technology-friendly, and high accuracy, but also suitable for path-finding researches on 5-nm node and beyond.

Design and analysis of INDEP FinFET SRAM cell at 7‐nm technology

AbstractThe reduction in size of metal oxide semiconductor (MOS) devices results in increase in leakage power dissipation, which occurs due to the short‐channel effects in subthreshold region. Now a day's power dissipation is one of the crucial issues that the modern electronic industry is facing. Fin‐type field‐effect transistor (FinFET) can be proven as a best substitute to reduce leakage power dissipation in logic circuits. Degradation of performance with process variations is of major concern and needs to design FinFET circuits with minimum leakage power dissipation. In this paper, static random‐access memory (SRAM) cell is designed using low power shorted‐gate (SG) FinFETs at 7‐nm technology to minimize leakage power dissipation besides improving other performance parameters like static noise margins (SNMs) and power delay product (PDP) as well. The various parameters are analyzed using butterfly and N‐curve methods. The ASAP7 PDK is used to design SRAM cells using Cadence Virtuoso tool. The simulated results show that FinFET input‐dependent (INDEP) technique reduces the leakage power dissipation by 32.08% and 13.50%, respectively, in read and write conditions of FinFET SRAM cell. The Monte‐Carlo simulation results show the reduction in average power using INDEP approach at ±10% process, voltage and temperature (PVT) variations under 3σ Gaussian distribution of FinFET SRAM cell.

A highly stable reliable SRAM cell design for low power applications

The growth in demand for power-efficient neural network accelerators has generated an intense demand for low power static random access memory (SRAM). In this context, a power-efficient transmission gate based 9-Transistor (TG9T) SRAM bitcell has been proposed in this work. In order to assess the relative performance of the proposed design in terms of major design metrics, it has been juxtaposed with contemporaneous designs such as the feedback-cutting 7T, fully differential 8T (FD8T) and single-ended disturb free 9T (SEDF9T) bitcells, while the reliability of such SRAM designs when subjected to process variations has also been analyzed. In terms of read stability (RSNM), the TG9T shows 2.87×/3.36× higher RSNM and 2.90×/2.67× narrower spread in RSNM, respectively, as compared to 7T/FD8T. In addition, it also exhibits 1.4×/6.55× higher write ability (WSNM) and 1.01×/5.05×/1.06× narrower spread in WSNM when compared with FD8T/SEDF9T and FD8T/SEDF9T/7T respectively. Moreover, a 1.15×/1.06× narrower spread in read delay (TRA) and 1.54×/1.38× narrower spread in read current (IREAD) are also exhibited by the proposed design in comparison with 7T/FD8T. The reliable nature of TG9T is indicated by the narrower spread in read stability, write ability, read delay and read current. Furthermore, in comparison with 7T/FD8T, TG9T consumes 2.92×/1.04× lower hold power. Additionally, the proposed cell shows 10.80×/17.81× lower write power consumption and 1.43×/18.37× lower read power consumption when compared to that of SEDF9T/FD8T and 7T/FD8T respectively. Amongst all SRAM bitcells used for comparison, the proposed bitcell yields the lowest VDD,min. The TG9T cell achieves all the aforementioned improvements at the cost of 1.22×/1.34× longer TWA and 1.93×/1.93× longer TRA when compared with 7T/SEDF9T and 7T/FD8T, respectively, at a supply voltage of 0.7 V.

Design and performance analysis of 6T SRAM cell on different CMOS technologies with stability characterization

With the advent of portable devices, the demand for static random-access memory (SRAM) is increasing with large use of SRAM in System on Chip and high-performance VLSI circuits. SRAM optimization has become a focal point for research work, as 60% to 70% area of the chip is consumed by the memories. The performance parameters optimization can lead to the overall optimization of the performance of the chip. In this paper design and analysis of the 6T SRAM cell at different technologies using PTM (Predictive Technology Model) model has done with the aim of reducing power dissipation while maintaining stability. Then the performance of SRAM cell is compared on the basis of power dissipation i.e. dynamic power dissipation and static power dissipation, delay, Power Delay Product (PDP) and Static Noise Margin (SNM).SRAM cell read stability and write-stability are major concerns in nanometer CMOS technologies, due to the progressive increase in intra-die variability and Vdd scaling. Cell stability is also examined by the calculation of SNM with the help of the butterfly curve method at different CMOS technologies. Effect of variation of channel length on static power consumption, dynamic power consumption, delay, PDP and SNM is also measured. SNM variation is also observed with the variation of the supply voltage.

Analytical modelling and design of 9T SRAM cell with leakage control technique

This paper presents a novel 9T static random access memory (SRAM) cell consisting of a single ended isolated read bit line with 2T read port for improving stability and a tail transistor for saving power. In the proposed design owing to the use of separate bitlines, the storing node voltage has not been affected during active mode operation. In the idle (hold) mode the static power dissipation of SRAM cell has been drastically reduced due to the formation of stack between tail transistor and internal latch. The proposed design has been verified by cadence virtuoso tool using UMC 65 nm CMOS technology. It provides a 42% and 34% improvement in write stability when compared to basic 6T and ultralow voltage (UV) 9T SRAM cells respectively. It has been observed that, the read stability is improved by 12% when compared to basic 6T SRAM cell and penalty of 10% when compared to UV 9T SRAM cell. A reduction of 22% in static power dissipation has also been observed in proposed design as compared to basic 6T SRAM cell when designed at same technology. This paper has also been proposed a mathematical modelling for validating the proposed design.

Energy optimization of 6T SRAM cell using low-voltage and high-performance inverter structures

The performance of the cell deteriorates, when static random access memory (SRAM) cell is operated below 1V supply voltage with continuous scale down of the complementary metal oxide semiconductor (CMOS) technology. The conventional 6T, 8T-SRAM cells suffer writeability and read static noise margins (SNM) at low-voltages leads to degradation of cell stability. To improve the cell stability and reduce the dynamic power dissipation at low- voltages of the SRAM cell, we proposed four SRAM cells based on inverter structures with less energy consumption using voltage divider bias current sink/source inverter and NOR/NAND gate using a pseudo-nMOS inverter. The design and implementation of SRAM cell using proposed inverter structures are compared with standard 6T, 8T and ST-11T SRAM cells for different supply voltages at 22-nm CMOS technology exhibit better performance of the cell. The read/write static noise margin of the cell significantly increases due to voltage divider bias network built with larger cell-ratio during read path. The load capacitance of the cell is reduced with minimized switching transitions of the devices during high-to-low and low- to-high of the pull-up and pull-down networks from VDD to ground leads to on an average 54% of dynamic power consumption. When compared with the existing ones, the read/write power of the proposed cells is reduced to 30%. The static power gets reduced by 24% due to stacking of transistors takes place in the proposed SRAM cells as compare to existing ones. The layout of the proposed cells is drawn at a 45-nm technology, and occupies an area of 1.5 times greater and 1.8 times greater as compared with 6T-SRAM cell.

Design of Novel SRAM Cell Using Hybrid VLSI Techniques for Low Leakage and High Speed in Embedded Memories

Static or leakage power is the dominating component of total power dissipation in deep nanometer technologies below 90 nm, which has resulted in increase from 18% at 130 nm to 54% at 65 nm technology due to continued device and voltage scaling. Static random access memory (SRAM) is a type of RAM in which data is not written permanently and it does not need to be refreshed periodically. Different techniques have been applied to SRAM cell to reduce leakage power without affecting its performance. A novel 10T SRAM architecture is proposed in this paper which operates in three modes (active, park, standby or hold). The main objective of the proposed architecture is to provide better stability and reduced delay in active mode, reduced leakage current in standby mode and retaining the logic state in park mode. Design metrics such as static and dynamic power, delay, power delay product, energy, energy delay product, rise and fall time, slew rate and static noise margin are taken into account. All the circuits were designed using SYNOPSYS EDA tool and simulated in 30 nm technology. Simulation results shows that the proposed SRAM is much better than conventional and other SRAM cells designed using hybrid techniques.

Energy Efficient Novel Design of Static Random Access Memory Memory Cell in Quantum-dot Cellular Automata Approach

This paper introduces a peculiar approach of designing Static Random Access Memory (SRAM) memory cell in Quantum-dot Cellular Automata (QCA) technique. The proposed design consists of one 3-input MG, one 5-input MG in addition to a (2×1) Multiplexer block utilizing the loop-based approach. The simulation results reveals the excellence of the proposed design. The proposed SRAM cell achieves 16% and 15% improvement in terms of total number of Cell counts and Area. Similarly, the proposed design structure realizes the overall power dissipation savings up to 35.3% at maximum energy dissipation of circuit, 38.6% at average energy dissipation of circuit, 36.1% at minimum energy dissipation of circuit, 36.4% at average energy dissipation of circuit and 40.1% at average switching energy dissipation compared to the latest reported designs. The power analysis and structural analysis of the proposed design is compared with its state-of-the-art counterpart designs, using QCAPro and QCADesigner 2.0.3 tools. The proposed QCA based SRAM cell design can be taken as a base design in building an ultra-low power information generating systems like Microprocessors.

Analysis of 6T SRAM Cell in Different Technologies

An important component of embedded cache memory of handheld digital devices is Static Random Access Memory (SRAM). It has become major data storage device due to its large storage density and less access time. The demand of low voltage low power SRAM has been raised by the exponential growth of low power digital devices. At low voltage operation of any device, the noise margin is another parameter that needs attention. This paper gives the design and implementation of 6T SRAM cell in 180nm and 90nm standard CMOS process technology. The simulation has been performed in Cadence Virtuoso environment. The performance analysis of SRAM cell has been evaluated in terms of Static Noise Margin (SNM).

Schmitt trigger-based single-ended 7T SRAM cell for Internet of Things (IoT) applications

The Internet of Things is an emerging application area which is going to become one of the leading electronic hubs in the semiconductor industry. The IoT systems require battery-enabled energy-efficient memory circuits to operate at ultra-low voltage (ULV). In this paper, a novel Schmitt trigger-based, single-ended 7-Transistor (7T) Static Random Access Memory (SRAM) cell which uses dynamic body bias technique for IoT applications is presented. The proposed 7T SRAM cell is designed using standard 45nm Complementary Metal Oxide Semiconductor technology at an ULV of 0.3V. The post-layout simulation results have shown more than 22% improvements in the Read Static Noise Margin and more than 44% write, 63% read energy savings in comparison with the conventional 6T cell, 7T, single-ended 8T, and Schmitt trigger 11T cell designs. The proposed design is also found to be stable at different process corners and supply voltages. A new quality metric SNM per unit Area to Energy Ratio which evaluates the overall performance of the SRAM cell design is calculated and is found to be highest for the proposed design.

Analysis of 6T SRAM Cell in Different Technologies

Static random access memory (SRAM) is an important component of embedded cache memory of handheld digital devices. SRAM has become major data storage device due to its large storage density and less time to access. Exponential growth of low power digital devices has raised the demand of low voltage low power SRAM. This paper presents design and implementation of 6T SRAM cell in 180 nm, 90 nm and 45 nm standard CMOS process technology. The simulation has been done in Cadence Virtuoso environment. The performance analysis of SRAM cell has been evaluated in terms of delay, power and static noise margin (SNM).

FinFET-based 6T SRAM cell design: analysis of performance metric, process variation and temperature effect

In this paper, we have proposed a FinFET-based 6T Static Random Access Memory (SRAM) cell. The proposed FinFET-based 6T SRAM cell offers better stability in terms of Static Noise Margin (SNM) and Read Noise Margin (RNM). During the read operations, SRAM cell stability analysis is based on the SNM because many memory errors may occur. Since SNM changes with each cell operation, a complete analysis of SNM in read mode is required. In this paper, we have looked into the SRAM cell SNM during read mode analysing various options to improve cell stability. These techniques are based on the transistor width, word-line, bit-line and supply voltage modulations. We showed that it is possible to improve the stability of SRAM cell during read operations, while reducing word-line voltage which reduces the leakage current. We have also analysed the temperature effect on SNM, leakage current and leakage power for FinFET-based SRAM cell.

Advances on Low Power Designs for SRAM Cell

As the development of complex metal oxide semiconductor (CMOS) technology, fast low-power static random access memory (SRAM) has become an important component of many very large scale integration (VLSI) chips. Lot of applications preferred to use the 6T SRAM because of its robustness and very high speed. However, the leakage current has increasing with the increase SRAM size. It consumes more power while in standby condition. The power dissipation has become an importance consideration due to the increase integration, operating speeds and the explosive growth of battery operated appliances. The objective of this paper is to review and discuss several methods to overcome the power dissipation problem of SRAM. Low power SRAM can be produced with improvement in term of power dissipation during the standby condition, write operation and read operation. Discharging and charging of bit lines consumes more power during write ‘0’ and ‘1’compared to read operation. One of the methods to produce low power SRAM design is with make modification circuit at a standard 6T SRAM cell. This modification circuit will help to decrease power dissipation and leakage current. Several method was discussed in this paper for understand the method to produce low power design of SRAM cell. Recommendations for future research are also set out. This review gives some idea for future research to improve the design of low power SRAM cell.

Strained SOI FINFET SRAM Design

Impact of strained silicon effects in double-gated FinFET structures on static random access memory (SRAM) cell functionality is presented. Three FinFET silicon-on-insulator (SOI) SRAM cell embodiments representing unstrained, strained, and NFET-only-strained devices are compared against a planar PDSOI SRAM cell design. The metrics encompass both static and dynamic behavior of the cell and are analyzed through 2-D process hardware-calibrated device models (Lg=25 nm). The key findings of this letter are: 1) PFET devices with tensile strain are found to degrade the FinFET cell Read Noise Margin and cell ability to write a strong “1”; 2) by restricting the tensile strain to the NFET devices FinFET SRAM cell Read stability and access times improve by 10%-20% relative to their unstrained FinFET and NFET-only strained PDSOI counterparts.

A highly reliable NBTI Resilient 6T SRAM cell

In this work, a highly reliable six-transistor (6T) Static Random Access Memory (SRAM) cell is proposed. The proposed SRAM cell is resilient to Negative Bias Temperature Instability (NBTI), since, PMOS pull-up transistors are replaced by their counterpart NMOS pull-up transistors. We compared the different parameters and performance indices (static noise margin and energy per operation) of the proposed SRAM cell with the standard 6T and loadless 4T SRAM cells. In order to achieve full logic level in the proposed SRAM cell, we studied the effect of PMOS as access transistors and compared with the loadless 4T SRAM cells with and without NBTI effect. It is observed that the proposed PMOS access transistors based SRAM cell yield better reliability (120% improvement in read SNM) with marginal increase in energy per operation as compared to NMOS access transistors. The leakage current of the proposed SRAM cell is 57× less than the 4T SRAM cell. The proposed SRAM cell design has positive impact of NBTI stress and yields significant improvement in the SRAM cell reliability as compared to its counterpart standard 6T SRAM cell.