Abstract
ABSTRACT In this letter, we propose a new design of an ultra-low-power and high performance six – transistor (6 T) static random access memory (SRAM) cell using graphene nanoribbon field-effect transistors (GNRFETs). HSPICE (Simulation Program with Integrated Circuit Emphasis)-compatible compact GNRFETs model is used to design and validate the different SRAM cells. The proposed cell improves the performance in terms of power consumption, read data stability, and writeability at the low supply voltage. The proposed cell also significantly reduces the leakage power consumption due to excellent control on the gate leakage current. The small bandgap and the high ratio in a GNRFET device show great potential for high-speed nanoelectronics applications. The cell consumes ultra-low power due to its capability to operate below 0.5 V, which makes it suitable for low power applications.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
