Static Logic Research Articles

A Low Power Digital Binary Magnitude Comparator Design for Very Large Scale Integration Applications

This paper reports two designs of low power digital binary magnitude comparator based on static complementary CMOS logic style. The designs make use of recently reported latest XNOR gate designs. The comparator designs proposed here are easily scalable for higher order bits and thus highly suitable for VLSI applications. Mathematical equations establishing the relation between input bit width and transistor count of the magnitude comparators have also been derived in this paper. For a 64 bit magnitude comparator, the designs proposed in this paper outperform an existing design by 12.17% and 10.42% in terms of transistor requirement and 14.81% and 11.78% in terms of average power consumption.

Pricing and Competition with 100% Variable Renewable Energy and Storage

Electricity production is a key sector in global decarbonization efforts, and variable renewable energy (VRE) technologies are a primary way to produce carbon-free electricity. We study an electricity market where generation is 100% VRE, while storage and elastic demand resolve temporal supply-demand imbalances. We model hourly market equilibrium to analyze price formation and imperfect, Cournot-type competition with varying levels of ownership concentration. Market power is exerted either with storage-only or with both VRE and storage. In such a system, prices are determined dynamically by demand and intertemporal storage decisions, breaking the static logic of “merit order” with dispatch-able generation. The numerical results indicate that market power with storage has a relatively moderate effect on prices and market efficiency. However, market power exerted with VRE has far larger welfare impacts, resulting from curtailed generation. However, such actions could be more readily observed by a regulator via monitoring.

Approaching the Design of Energy Recovery Logic Circuits Using TFETs

Reducing supply voltage is an effective way to reduce power consumption, however, it greatly reduces CMOS circuits speed. This translates in limitations on how low the supply voltage can be reduced in many applications due to frequency constraints. In particular, in the context of low voltage adiabatic circuits, another well-known technique to save power, it is not possible to obtain satisfactory power-speed trade-offs. Tunnel field-effect transistors (TFETs) have been shown to outperforms CMOS at low supply voltage in static logic implementations, operation due to their steep subthreshold slope ( SS ), and have potential for combining low voltage and adiabatic. To the best of our knowledge, the adiabatic circuit topologies reported with TFETs do not take into account the problems associated with their inverse current due to their intrinsic p-i-n diode. In this article, we propose a solution to this problem, demonstrating that the proposed modification allows to significantly improving the performance in terms of power/energy savings compared to the original ones, especially at medium and low frequencies. In addition, we have evaluated the relative advantages of the proposed TFET adiabatic circuits with respect to their static implementations, demonstrating that these are greater than for FinFET transistor designs.

A New ALU Design using PNS-FCR: Static CMOS Logic for Microprocessors

Arithmetic Logic Unit (ALU) is the main component in the processors. Most important design consideration in integrated circuit is power. In all the components of ALU data path is the active one and it consumes more percent of power in the total power. In the modern microprocessors it is important to have power efficient data paths. To reduce the power consumption in microprocessors the ALU is designed using PNS-FCR static CMOS logic. In this paper static CMOS logic is used to reduce power consumption. Static technique does not need any clock. So it leads to less power consumption. For the implementation of the ALU with the PNS-FCR static logic mentor graphics tool is used. The power consumption of ALU is compared with and without using FCR. An 8-bit ALU is designed in mentor graphics with 130nm technology. The proposed design methodology gives less power consumption.

Design of Manchester Carry Chain Adder using High speed Domino Logic

Dynamic logic circuits are preferred over static logic circuits for their increased speed performance and lower power consumption. However, they are found prone to false evaluation while cascading multiple stages of dynamic logic circuits. To overcome this problem, the domino logic circuits were proposed by researchers. However, they offer reduced noise margins due to increased leakage current and charge sharing problems. In this paper, Manchester Carry Chain Adder design is explored for use with domino logic and comparison of various domino logic topologies intended for improved noise immunity and reduced leakage current against the proposed structure have been carried out. Wide fan-in gates and 8-bit Manchester Carry Chain Adder (MCC) based on various high speed domino logic circuit topologies have been designed using Cadence® using 180nm technology library from TSMC. Design of 8-bit OR gate, using High Speed Domino (HSD) topology consumes 10.8% lower power in comparison with Controlled-Current Comparison-based domino logic (C3D) topology. Furthermore, it is observed that an 8-bit Manchester Carry Chain adder using HSD topology is 5.027 times faster than C3D topology and the leakage power consumption is also reduced.

Electrical Stability Analysis of Dynamic Logic Using Amorphous Indium–Gallium–Zinc-Oxide TFTs

Prior research has reported that the device characteristics of amorphous indium–gallium–zinc-oxide (a-IGZO) thin-film transistors (TFTs) have been changed by instabilities due to electrical stress. Because positive bias stress and high current stress produce a positive threshold voltage shift, if the digital logic circuit is designed using a-IGZO TFTs, there is a high possibility that the circuit suffers from malfunction. In this letter, the dynamic and the static logic circuits using n-type a-IGZO TFTs are compared in terms of stability for electrical stress. In order to compare the stability of the two circuits, DC and AC signals are applied. The measurement results suggest that the dynamic logic circuit is much more stable than the static logic circuit regarding electrical stress.

Theory of Expansion Boolean Algebra and Its Applications in CMOS VLSI Digital Systems

Based on the relationship between circuits (systems) and the signals in the circuits (systems), the theory of expansion Boolean algebra is presented in this paper. Static complementary logic circuits and static pass transistors logic circuits have been used to implement the high-speed and low-power-consumption cells circuits in CMOS VLSI systems. It is important to study the extraction method of logic expressions for these types of circuits. By analyzing the operations principles of MOS transistors in CMOS circuits, the theory of expansion Boolean algebra of CMOS logical circuits is presented. Based on the algebraic theory, a method of extracting the logic expressions from the two types of CMOS logical circuits is derived. On the basis of the method, a switch-level design method of CMOS logic circuits based on the algebra theory is presented, and the design method is used to design the high-speed and low-power full adder cells in CMOS VLSI systems. By the results of the simulation experiments, it is shown that the pass transistors and transmission gates hybrid CMOS full adder circuits proposed in this paper have a lower power-delay product by comparison with the full adder circuits designed by using other methods.

Multi-unit dynamic PRA

Dynamic Probabilistic Risk Analysis (PRA) methods couple stochastic methods (e.g., RAVEN) with safety analysis codes (e.g., RELAP5-3D) to determine risk associated to complex systems such as nuclear plants. Compared to classical PRA methods, which are based on static logic structures (e.g., Event-Trees, Fault-Trees), they can evaluate with higher resolution the safety impact of timing and sequencing of events on the accident progression. Recently, special attention has been given to nuclear plant sites which consist of multiple units and, in particular, on the safety impact of system dependencies, shared systems and common resources on core damage frequencies. In the literature, classical PRA methods have been employed to model multi-unit sites in a limited number of cases while Dynamic PRA methods have never been applied to analyze a full multi-unit model. This paper presents a PRA analysis of a multi-unit plant using Dynamic PRA methods. We employ RAVEN as stochastic tool coupled with RELAP5-3D. The site under consideration consists of three units (each unit is composed by a reactor and its associated spent fuel pool) while the considered initiating event is a seismic induced station blackout event. This paper describes in detail how the multi-unit site has been constructed and, in particular, how unit dependencies and shared resources are modeled from both a deterministic and stochastic point of view.

A Review of Constant Delay Logic at 90nm CMOS Technology

This paper presents the review work on Constant Delay (CD) Logic. Dynamic (Complementary Metal Oxide Semiconductor) CMOS circuit style is introduced which allows to reduce number of transistors for implementing any logic. (Feed Through Logic) FTL overcomes the use of more transistors in dynamic domino logic, this use implement using the same number of transistors required in dynamic logic. The CD Logic generates the high speed of operation of possible circuits. The timing window technique is analyzed which is mainly for the reduction of power dissipation i.e., reduction of the evaluation time. CD Logic display a rare aspect where the output is pre-evaluated before the input from the previous stage is ready. This property offers good performance analysis over the dynamic and static logic style.CD Logic reducing the charging current with the support of Leakage current. Using 90nm CMOS technology, different circuits based on CD Logic is analyzed for power, delay, (Power Delay Product) PDP and noise calculation.

A mixed model to evaluate random hardware failures of whole-redundancy system in ISO 26262 based on fault tree analysis and Markov chain

In order to ensure safety and reliability, some safety-related electrical and electronic (E/E) systems in vehicles need to be designed as a whole-redundancy system. Although ISO 26262 provides guidance for the analysis of random hardware failure, the problem of estimating whether the safety-related E/E systems, especially whole-redundancy system can meet the index of the ASIL level in ISO 26262 is still unsolved. Fault tree analysis (FTA) is one of the basic methods to analyze random hardware failure of a vehicle’s E/E systems quantitatively. In generic FTA, the quantitative analysis of dynamic logic gates, which usually exist in the fault tree of whole-redundancy system, cannot be calculated. Meanwhile, Markov chain can solve the problem of quantitative calculation of dynamic fault tree, but brings a side-effect of complicating the calculation of static logic gates in fault trees. In order to evaluate random hardware failure of a vehicle E/E system more concisely and effectively, and to estimate if a new safety-related E/E system’s random hardware failure rate can meet the index demand in ISO 26262, this study proposed a mixed model based on FTA and Markov chain. First, the definition of random hardware failure and fault classification were clarified. Then, a mixed model based on FTA and Markov chain was proposed. Finally, a whole-dual-redundancy steer by wire system was used as an example to test the validity of the mixed model. This study not only proposed a new mixed model based on FTA and Markov chain for the calculation of a whole-redundancy system’s random hardware failure rate, but also provided a new quantitative validation method for safety-related E/E systems in vehicles that need to meet the reliability index requirement in ISO 26262.

A Novel Reconfigurable Sub-0.25-V Digital Logic Family Using the Electron-Hole Bilayer TFET

We propose and validate a novel design methodology for logic circuits that exploits the conduction mechanism and the presence of two independently biased gates (“n-gate” and “p-gate”) of the electron-hole bilayer tunnel field-effect transistor (EHBTFET). If the device is designed to conduct only under certain conditions, e.g., when $V_{\mathrm {n-gate}} = V_{\mathrm {DD}}$ and $V_{\mathrm {p-gate}} = 0$ , it then shows an “XOR-like” behavior that allows the implementation of certain logic gates with a smaller number of transistors compared to conventional CMOS static logic. This simplifies the design and possibly results in faster operation due to lower node capacitances. We demonstrate the feasibility of the proposed EHBTFET logic for low supply voltage operation using mixed device/circuit simulations including quantum corrections.

Tunnel Transistor-Based Reliable and Energy Efficient Computing Architectures with Circuit and Architectural Co-Design at Low VDD

Tunnel field-effect transistors (TFETs) as low voltage device options have attracted recent attention for energy efficient circuit designs with CMOS technology scaling. This paper presents the circuit and architectural co-design approach for designing reliable and energy efficient architectures (adder cells) for new computing platforms at supply voltages. At circuit level TFET-based 28-transistor static logic design (28T) and 24-transistor transmission gate logic design (24T) have been explored. At architectural level, multiplexer (MUX)-based 22-transistor full adder design (22T) is proposed. Performance of TFET-based architectures have also been benchmarked with 20[Formula: see text]nm double gate Si FinFET technology. It has been seen that with FinFET technology 24T design is not effective in terms of energy efficiency and reliability (due to the large leakage currents in transmission gate logic topology). 28T design is the best in reliability perspective (in terms of reduced over shoots, full logic swing and reduced glitch duration etc.) and 22T design to be energy efficient option. It has been demonstrated in this paper that TFET’s steep slope characteristics enable the 24T design to have similar reliability characteristics like 28T design and energy efficiency like 22T design. TFET-based 22T design has [Formula: see text]91% smaller energy delay product (EDP) and [Formula: see text]84.4% less power delay product (PDP) in comparison to the low threshold voltage (LVT) FinFET 22T design at 0.2[Formula: see text]V VDD.

Dynamic Logic Circuits Using a-IGZO TFTs

Previously reported thin-film transistor (TFT) digital logic gates are mostly static circuits. If the static logic circuits are implemented using either nMOS or pMOS technologies alone, unlike CMOS technologies, the circuits consume high power because of the steady-state current, and take large circuit area. In this paper, the dynamic logic circuits using n-type a-IGZO TFTs are proposed to resolve the power and circuit area issues. The dynamic logic circuits such as inverters and nand gates are fabricated in an amorphous indium–gallium–zinc–oxide TFT technology, and traditional static logic circuits are also implemented with the same technology for comparison purposes. The measurement results show that the proposed dynamic logic circuit consumes no steady-state current, and the circuit area is reduced by 93.1%.

New Light Weight Threshold Voltage Defined Camouflaged Gates for Trustworthy Designs

The outsourcing of the IC fabrication process introduces the security vulnerabilities into the design. An attacker can exploit them to extract the functionality using image processing-based reverse engineering and can also mount the various attacks such as hardware Trojan, piracy, overbuilding, etc. Various dummy contacts and Threshold Voltage Defined (TVD) logic-based layout camouflaging techniques are presented that can deceive the attacker into incorrectly interpreting the functionality of the camouflaged gate. The existing dummy contact-based techniques require large overhead and provide poor security whereas, the TVD logic-based camouflaging techniques increase the security at the cost of large area and energy overhead. Therefore, in this paper, new light weight TVD static and dynamic logic (TVD-SL and TVD-DL) based camouflaged gates are proposed. The proposed TVD-SL/DL gates have same physical structure and provide the functionality of several standard gates by implanting different threshold voltages during manufacturing. Further, various simplified TVD-SL/DL gates are also proposed to achieve the overhead and security trade-off. To evaluate the efficacy, the proposed TVD logic gates are implemented using 32nm PTM library and simulated using the HSPICE simulator. The simulation results show that the proposed TVD-SL-based gates on an average reduce 35.49%, 59.18% and 72.05% whereas the proposed TVD-DL reduces 54.84%, 84.18% and 82.30% area, power and delay respectively over the existing. Further, on an average, the proposed TVD-DL-based camouflaged gates require 56% less power over the standard gates. Due to the low-cost and high energy efficiency, the proposed logic gates are best suited for the development of secure and portable devices for the Internet of Things applications.

Interactive Logic Models: Using Design and Technology to Explore the Effects of Dynamic Situations on Program Logic

Logic models are commonly used by evaluators to illustrate relationships among a program's inputs, activities, outputs, and outcomes. They are useful in helping intended users develop programs, communicate a program's theory of change, and design evaluations. However, as static documents, logic models can be challenging to build, work with, and present to stakeholders, especially for large and complex programs. Challenged by this inadequacy of static logic models, a program evaluator turned to a graphic designer and a software developer for help. Together, this interdisciplinary group developed web-based software (Dylomo) that allows evaluators to create logic models that better communicate the logic within the model. In this paper, we describe the process by which this interdisciplinary group created this new technology—including a user-testing experience at the Canadian Evaluation Society Conference in Canada in June 2016—to build and present logic models that use interactivity and allow program evaluators to more easily demonstrate the logic within a complex program and to visually explore the potential effects of changes within the program's landscape. This software is freely available on the web, so readers can apply it to their own evaluation practice.

A novel high-speed CMOS circuit based on a gang of capacitors

ABSTRACTThere is no doubt that complementary metal-oxide semiconductor (CMOS) circuits with wide fan-in suffers from the relatively sluggish operation. In this paper, a circuit that contains a gang of capacitors sharing their charge with each other is proposed as an alternative to long N-channel MOS and P-channel MOS stacks. The proposed scheme is investigated quantitatively and verified by simulation using the 45-nm CMOS technology with VDD = 1 V. The time delay, area and power consumption of the proposed scheme are investigated and compared with the conventional static CMOS logic circuit. It is verified that the proposed scheme achieves 52% saving in the average propagation delay for eight inputs and that it has a smaller area compared to the conventional CMOS logic when the number of inputs exceeds three and a smaller power consumption for a number of inputs exceeding two. The impacts of process variations, component mismatches and technology scaling on the proposed scheme are also investigated.

Static logic state analysis by TLS on powered logic circuits: Three case studies for suspected stuck-at failure modes

Thermal Laser Stimulation (TLS) for static logic state analysis is applied to failure analysis. Three case studies of analyses of the digital logic in an automotive Application Specific Integrated Circuit (ASIC) are discussed. By analyzing the logic states of the circuit we were able to identify the mechanism and localize the site of irregular behavior non-destructively, both for a stuck-at fault and two weak interconnects. The approach measures the power supply current while applying TLS to the device back side. This allows an extremely high analysis coverage, because every transistor is connected to the power supply, making this method a universal tool for every digital circuit failure analysis (FA) workflow, because the gained understanding of the fault allows to replace multiple steps of alternative FA techniques by only a single technique, reducing time and cost for successful FA.

Design of Low Power and High Performance Phase Locked Loop using Dual Mode Logic

The Phase Locked Loop has wide variety of application such as frequency synthesizers, tracking satellite, and demodulation in telecommunication; it needs to operate with low power. When the static logic is used in PLL, it operates with low power consumption but increases delay. When it operates in dynamic logic it consumes more power but the speed of operation increases. In order to attain both the advantages of static and dynamic logic, Dual Mode Logic method is proposed in the design. In Dual Mode Logic, the circuit operates both in static and dynamic modes of operation. In static mode, saves power and in dynamic mode the performance increases. The simulation is performed with the 180nm CMOS technology and the result shows that the suggested method yields reduced power consumption and computational delay when compared with the CMOS logic.

A Standard-Cell-Design-Flow Compatible Energy-Recycling Logic With 70% Energy Saving

This paper presents an energy-recycling micro-architecture and the associated adiabatic logic for ultra-low energy applications, such as implantable bioelectronics. The proposed design achieves low power by transferring and recycling energy between digital logic blocks along with the signal propagation. The CMOS-like layout methodology allows the adiabatic logic core to be synthesized and auto-placed-and-routed with current EDA tools for complex digital systems. A 50% energy saving can be achieved for up to 100 MHz compared to conventional static CMOS logic. As a proof of concept, a 14-tap 8-bit finite impulse response (FIR) filter has been implemented in 90-nm CMOS for implantable neural signal processing. With only 16% area overhead compared to the static CMOS counterpart, the proposed design achieves 70% to 53% of energy reduction for 87 kHz to 410 kHz from a 1 V supply. The FIR filter realized with the proposed energy-recycling logic achieves an FoM of 5.33 nW/MHz/Tap/In-bit/Coeff-bit, yielding a 1.9 $\times$ to 42 $\times$ higher energy efficiency than the state-of-the-art custom energy-efficient FIR designs.

Design of Low Power High Speed Digital Multiplier using Double Threshold Voltage Adder Module

An increased twin threshold voltage management technique has been projected during this paper. Scaling associate degreed power reduction trends in future technologies can cause sub threshold outflow currents to become a more and more giant part of total power dissipation. This paper presents dual-threshold voltage techniques for reducing standby power dissipation whereas still maintaining high performance in static and dynamic combinable logic blocks by selection putting the high threshold voltage, the outflow ought to be reduced by over ten times, whereas at a similar time achieving comparable performance. This method is employed in a very small meter technology. Simulation results show that the facility consumed has been reduced by over ten times. The speed is even quicker than associate degree all low-Vt implementation. As wireless communications demand devices with terribly long battery life, low power style is turning into a lot of and a lot of necessary every day. This is often true for not solely moveable devices, however additionally different applications. Once microprocessors are becoming a lot of and a lot of powerful, low power style is required to alleviate the matter of warmth dissipation also.