Design of Low Power High Speed Digital Multiplier using Double Threshold Voltage Adder Module

Abstract

An increased twin threshold voltage management technique has been projected during this paper. Scaling associate degreed power reduction trends in future technologies can cause sub threshold outflow currents to become a more and more giant part of total power dissipation. This paper presents dual-threshold voltage techniques for reducing standby power dissipation whereas still maintaining high performance in static and dynamic combinable logic blocks by selection putting the high threshold voltage, the outflow ought to be reduced by over ten times, whereas at a similar time achieving comparable performance. This method is employed in a very small meter technology. Simulation results show that the facility consumed has been reduced by over ten times. The speed is even quicker than associate degree all low-Vt implementation. As wireless communications demand devices with terribly long battery life, low power style is turning into a lot of and a lot of necessary every day. This is often true for not solely moveable devices, however additionally different applications. Once microprocessors are becoming a lot of and a lot of powerful, low power style is required to alleviate the matter of warmth dissipation also.