Triple-Threshold Static Power Minimization Technique in High-Level Synthesis for Designing High-Speed Low-Power SOC Applications Using 90nm MTCMOS Technology

Abstract

This paper reports a novel triple-threshold static power minimization technique in high-level synthesis of highspeed low-power SOC applications. Using 90 nm multi-threshold CMOS (MTCMOS) technology, we evaluate the performance and power dissipation of benchmark circuits synthesized using transistors with different threshold voltages. Using static timing analysis, we determine the timing requirements of cells and place cells with low and standard threshold voltages in the critical paths. Cells with a high threshold voltage are placed in non-critical paths to minimize the static power with no overall timing degradation. From the timing and power analysis, we determine the optimal placement of high, standard and low threshold voltage cells. Applying the new triple-threshold technique to optimize 20 circuits originating from the ISCAS'99 benchmark, we have achieved an average saving of 85.3% in the static power compared to conventional all-LVT circuits, and 39.6% saving compared to the dual-threshold (HVT+LVT) technique.