Design of Low Power Digital Multiplier Using Dual Threshold Voltage Adder Module

Abstract

An enhanced dual threshold voltage control technique has been proposed in this paper. Scaling and power reduction trends in future technologies will cause sub threshold leakage currents to become an increasingly large component of total power dissipation. This paper presents dual-threshold voltage techniques for reducing standby power dissipation while still maintaining high performance in static and dynamic combinational logic blocks By selectively placing the high threshold voltage, the leakage should be reduced by more than 10 times, while at the same time achieving comparable performance. This technique is used in a micro meter technology. Simulation results show that the power consumed has been reduced by more than 10 times. The speed is even faster than an all low-Vt implementation. As wireless communication demands devices with very long battery life, low power design is becoming more and more important each day. This is true for not only portable devices, but also for other applications. When microprocessors are getting more and more powerful, low power design is needed to relieve the problem of heat dissipation as well.