An algorithm for reducing leakage power dissipation in combinational digital designs using dual threshold voltages

Abstract

For CMOS-based nanometer technology, leakage power dissipation became an important issue in low power design. An approach to deal with this problem for timing constrained digital designs is to use dual threshold voltages. A low threshold voltage is used for computational elements on critical paths to satisfy timings, while a high threshold voltage can be used for the other elements off critical paths to reduce leakage power. The problem of assigning high threshold voltages to reduce leakage power under timing constraints is an NP-hard problem. In this paper, we present an approximate polynomial-time algorithm to address this problem. We also provide a Mixed Integer Linear Program (MILP) which optimally solves the problem for small designs. The proposed approach is compared with existing ones. Obtained experimental results are provided.