A Review of Constant Delay Logic at 90nm CMOS Technology

Abstract

This paper presents the review work on Constant Delay (CD) Logic. Dynamic (Complementary Metal Oxide Semiconductor) CMOS circuit style is introduced which allows to reduce number of transistors for implementing any logic. (Feed Through Logic) FTL overcomes the use of more transistors in dynamic domino logic, this use implement using the same number of transistors required in dynamic logic. The CD Logic generates the high speed of operation of possible circuits. The timing window technique is analyzed which is mainly for the reduction of power dissipation i.e., reduction of the evaluation time. CD Logic display a rare aspect where the output is pre-evaluated before the input from the previous stage is ready. This property offers good performance analysis over the dynamic and static logic style.CD Logic reducing the charging current with the support of Leakage current. Using 90nm CMOS technology, different circuits based on CD Logic is analyzed for power, delay, (Power Delay Product) PDP and noise calculation.