Static Logic Research Articles

Sense Amplifier Half-Buffer (SAHB): A Low-Power High-Performance Asynchronous Logic QDI Cell Template

We propose a novel asynchronous logic (async) quasi-delay-insensitive (QDI) sense-amplifier half-buffer (SAHB) cell design approach, with emphases on high operational robustness, high speed, and low power dissipation. There are five key features of our proposed SAHB. First, the SAHB cell embodies the async QDI 4-phase ( $4\phi )$ signaling protocol to accommodate process-voltage–temperature variations. Second, the sense amplifier (SA) block in SAHB cells embodies a cross-coupled latch with a positive feedback mechanism to speed up the output evaluation. Third, the evaluation block in the SAHB comprises both nMOS pull-up and pull-down networks with minimum transistor sizing to reduce the parasitic capacitance. Fourth, both the evaluation block and SA block are tightly coupled to reduce redundant internal switching nodes. Fifth, the SAHB cell is designed in CMOS static logic and hence appropriate for full-range dynamic voltage scaling operation for $\text{V}_{\mathrm {\mathbf {DD}}}$ ranging from nominal voltage (1 V) to subthreshold voltage ( $\sim 0.3$ V). When six library cells embodying our proposed SAHB are compared with those embodying the conventional async QDI precharged half-buffer (PCHB) approach, the proposed SAHB cells collectively feature simultaneous $\sim 64$ % lower power, $\sim 21$ % faster, and $\sim 6$ % smaller IC area; the PCHB cell is inappropriate for subthreshold operation. A prototype 64-bit Kogge-Stone pipeline adder based on the SAHB approach (at 65 nm CMOS) is designed. For a 1-GHz throughput and at nominal $\text{V}_{\mathrm {\mathbf {DD}}}$ , the design based on the SAHB approach simultaneously features $\sim 56$ % lower energy and $\sim 24$ % lower transistor count advantages than its PCHB counterpart. When benchmarked against the ubiquitous synchronous logic counterpart, our SAHB dissipates $\sim 39$ % lower energy at the 1-GHz throughput.

Layout-based Single Event Mitigation Techniques for Dynamic Logic Circuits

Due to the intrinsic lack of restoring paths, dynamic logic circuits have significant single-event susceptibility, and thus, they are not preferred in applications requiring high reliability when compared to static logic. However, in high speed applications, this circuit family is still very attractive. This papers presents two layout-based single-event resilient dynamic logic designs. The resultant SET pulse is suppressed because of charge-sharing in the layout-level. Simulation results verify that they enjoy higher single event tolerance. Experimental results validate the fact that approximately 20?~?30 % of magnitude reduction in cross-section is achieved in both designs. On the other hand, the increase in single-event performance is achieved at the expense of power and area overheads of 10 and 15 %, respectively, using our layout style in 130 nm CMOS bulk technology.

Delay and Performance Estimation for a 4-bit Even Parity Bit Generator Using the Logical Effort Model

Recent digital applications require high speed and high performance designs. The circuit design can be implemented using different types of logic gates. The logic gates are classified into two types; primitive and compound (complex) gates. Any complex logic circuit diagram can be converted into primitive using one type of universal gates; such as the NAND gates or the NOR gates only. The combinational circuits and any functional block can also be implemented using the NAND or the NOR gates only. This article shows how to build a 4-bit even parity bit generator using both universal gate types: the implementation using NAND gates only and the implementation for the 4-bit even parity bit generator using NOR gates only. A performance comparison between these two implementations, with different output loads in each case, is achieved to study the impact of the output load on the circuit delay. It will also determine which type of universal gates can be used to get better performance (delay) readings by using the logical effort technique. The logical effort is a technique used to estimate the static logic circuit delay and the power dissipated by a circuit. It helps designers make their right decisions about the delay and the power for a given design before the real implementation begins.

A CMOS-Based Dual Logic Mode Gate for Analysis of Logical Effort in Sequential and Combinational Circuit

Newly, a novel Dual Mode Logic (DML) family is utilized in the proposed technology. This logic performs operation in two modes, namely static and dynamic modes. DML gates can be swapped between the modes on-the-fly, which has very low power dissipation inthe static mode and high performance in the dynamic mode. A typical DML gate is very simple and has static logic family gate and an extra clocked transistor. The logical effort (LE) method is applied in the CMOS-based DML family. This method allows path length reduction, delay optimization and estimation of DML logic. In the existing system, the output attained from the multiplier and D-flip flop has less accuracy and high delay. In the proposed work, DML is designed based on CMOS to improve the accuracy. DML is established in multiplier and D-flip flop, which efficiently decreases the delay and energy dissipation. The LE is computed for both DML based multiplier and DML D-flip flops of the registers. The proposed framework provides better accuracy and has less delay and power dissipation when compared to the multiplier and D-flip flop without DML logic.

Performance Improvement of ALU using D3L Logic

Today's electronic circuits utilizes large amount of data and so a large number of processing elements. Usually, the overall system performance depends on the interconnection scheme and the individual processing element. The performance of individual processing elements depends on the logic by which it is implemented. There are different logic styles like static NMOS, CMOS, dynamic logic etc. introduced to implement digital circuits. Dynamic logic is distinguished from so-called static logic in that dynamic logic uses a clock signal in its implementation of combinational logic circuits and hence there is clock power dissipation. It was in 2000 R.Rufati, S.M Fukhraie and K.C Smith introduced D3L logic. They proved that D3L logic reduces clock power dissipation in dynamic circuits. Later they implemented a barrel shifter using D3L logic. The question is whether D3L logic can be used in place of static logic to improve the performance.

An optimal scheduling for using chain technique on superscalar processor

Increasing instruction level parallelism is one basic way to improve the performance of superscalar processors. True data dependency is the first issue to address when it comes to increasing the performance of the processor. The chain technique, which bypasses the execution result from one arithmetic logic unit to others, is an effective method to reduce the true data dependency without using a high frequency clock. We have developed an optimal scheduling for the chain technique that uses dependency maps to store the data dependency information and utilise it to issue the chained instructions effectively. The experimental results show that the chain technique improves the performance from about 2% to 25% in CommBench and SPECint2000. The hardware configuration shows that our proposed scheduling can be implemented using just static random access memories and small-scale control logics, with no need for larger scale hardware.

Low-power Super-threshold FinFET Domino Logic Circuits for High- Speed Applications

Domino logic circuits have faster operating speed than commonly used static logic ones, because they have lower input capacitances and no contention during transition. However, Domino logic circuits have more power dissipa- tion than static logic ones, since their clock tress with high switch activity dissipates large energy. A low-power super- threshold computing scheme is proposed to reduce power dissipations of FinFET Domino logic circuits. The pull-down transistors of all FinFET Domino circuits are configured in parallel, and thus improve operating speed. Unlike near- threshold circuits, super-threshold ones are supplied by much a larger supply voltage than the threshold voltage, but it is lower than the standard supply voltage. Super-threshold FinFET logic circuits can attain low power consumption with fa- vorable performance, because FinFET devices operating on medium strong inversion regions can provide better drive strength than conventional CMOS ones. The basic Domino logic gates are compared with static logic ones in terms of en- ergy consumption, delay, energy delay product (EDP), and maximum operation frequency with different voltages from near-threshold to super-threshold regions. All circuits are simulated with HSPICE at a PTM (Predictive Technology Mod- el) 32nm FinFET technology. The results show that the Domino gates can operate faster than static ones. In addition, it is also shown that Domino gates exhibit the best EDP in super-threshold regions (about 700mV). Compared with the stand- ard supply voltage of 1.0 V, the Domino gates supplied by 0.8V can attain energy reductions of more than 38.3% with a small performance penalty of about 14%.

Ambipolar Independent Double Gate FET (Am-IDGFET) for the Design of Compact Logic Structures

Among potential candidates to replace the CMOS transistor channel, several materials such as CNTs, GNRs, and SiNW show an interesting behavior known as “Ambipolarity.” Ambipolarity, means that n- and p-type behavior can be observed in the same device. By adding a fourth terminal to control the ambipolarity, a new category of devices has seen the light under the name of Ambipolar Independent Double Gate FETs “Am-IDGFETs.” These devices are capable of operating as either n-type or p-type switches according to their back-gate bias voltage. As a result, more options are available with no counterparts in CMOS technology. Based on Am-IDGFETs, we propose a circuit design approach to achieve compact logic structures by merging every two transistors in series structure using the in-field controllability via the back-gate of ambipolar devices. The approach is demonstrated for two logic styles: with a complementary static logic design style, it demonstrates an efficiency that can improve the compactness of logic structure by a factor of 2x, while with a dynamic logic style, a gain of 30% in terms of transistors count is achieved for a variety of application scenarios. We evaluate the performances of circuits designed from this approach in a case study focused on double gate carbon nanotube FET technology. Simulations results show that, with respect to conventional CMOS-16 nm gates and for comparable power consumption, time delay and integration density can both be improved by a factor of 2x and 2.5x, respectively. The power-delay-product is improved by 30%.

Genetic programming for smart phone personalisation

Personalisation in smart phones requires adaptability to dynamic context based on user mobility, application usage and sensor inputs. Current personalisation approaches, which rely on static logic that is developed a priori, do not provide sufficient adaptability to dynamic and unexpected context. This paper proposes genetic programming (GP), which can evolve program logic in realtime, as an online learning method to deal with the highly dynamic context in smart phone personalisation. We introduce the concept of collaborative smart phone personalisation through the GP Island Model, in order to exploit shared context among co-located phone users and reduce convergence time. We implement these concepts on real smartphones to demonstrate the capability of personalisation through GP and to explore the benefits of the Island Model. Our empirical evaluations on two example applications confirm that the Island Model can reduce convergence time by up to two-thirds over standalone GP personalisation.

Gate Stack Resistance and Limits to CMOS Logic Performance

The input resistance of CMOS circuits is a measurable limit on the performance of typical static CMOS logic gates. A survey of measured data from five generations of CMOS technology including polysilicon oxynitride gate first stacks (P-SiON), high K metal gate first stacks (GF), and high K replacement metal gate stacks (RMG) shows a trend of increasing gate resistance. We show DC and RF measurements may be analyzed to determine horizontal and vertical components of gate resistance in terms of scalable parameters and the sum of these components may be represented by a compact scalable equation representing total gate resistance. Measured noise data supports this decomposition. Gate resistance increases at advanced nodes and affects typical logic performance of a 20 nm replacement gate technology.

Logical Effort for CMOS-Based Dual Mode Logic Gates

Recently, a novel dual mode logic (DML) family was proposed. This logic allows operation in two modes: 1) static and 2) dynamic modes. DML gates, which can be switched between these modes on-the-fly, feature very low power dissipation in the static mode and high performance in the dynamic mode. A basic DML gate is very simple and is composed of any static logic family gate and an additional clocked transistor. In this paper, we introduce the logical effort (LE) methodology for the CMOS-based DML family. The proposed methodology allows path length minimization, delay optimization, and delay estimation of DML logic. This is done by development of complete and approximated LE models, which allows easy extraction of design optimization parameters, such as optimum number of stages, gates sizing factors, and delay estimations. The proposed optimization is shown for the dynamic mode of operation. Theoretical mathematical analysis is presented, and efficiency of the proposed methodology is shown in a standard 40-nm CMOS process.

Comparative Analysis Domino Logic Based Techniques For VLSI Circuit

Domino logic is a CMOS-based evolution of the dynamic logic techniques  based on either PMOS or NMOS transistors. Domino logic technique is widely used in modern digital VLSI circuit. Dynamic logic is twice as fast as static CMOS logic because it uses only N fast transistors. The Dynamic (Domino) logic circuit are often favored in high performance designs because of the high speed and low area advantage.Four different dynamic circuit techniques including Basic domino logic circuit are compared in this paper for low power consumption and speed of domino logic circuits. For digital circuit simulation used BSIM(Berkeley Short Channel IGFET ) Model because it control leakage current.

A 167-ps 2.34-mW Single-Cycle 64-Bit Binary Tree Comparator With Constant-Delay Logic in 65-nm CMOS

A single-cycle tree-based 64-bit binary comparator with constant-delay (CD) logic realized in a 65-nm, 1-V CMOS process is presented in this paper. Unlike dynamic logic yet domino-compatible, CD logic predischarges the output to logic “0” and conditionally makes a transition to logic “1” through the critical-path CLK PMOS transistors for an NMOS transistor network. The constant delay (regardless of the fan-in) feature makes it up to 2× faster than a dynamic logic gate during the D-Q mode for a complex logic such as a two-bit binary comparator. The proposed comparator's architecture is divided into two stages, where the first stage adapts a novel tree comparator structure specifically designed for static logic to achieve low-power consumption and the second stage utilizes CD logic to realize high performance without sacrificing the overall energy efficiency. At 1-V supply, the proposed comparator's measured delay is 167 ps, and has an average power and a leakage power of 2.34 mW and 0.06 mW, respectively. At 0.3-pJ iso-energy or 250-ps iso-delay budget, the proposed comparator with CD logic is 20% faster or 17% more energy-efficient compared to a comparator implemented with just the static logic.

Architecture Design of the Cladding Part Modeling System

The cladding part is a new type of layered heterogeneous material part with three layers of the substrate, the interface and the clad. According to the part unique material composition and structural characteristic, based on the hierarchical modeling method, the software architecture design of the cladding part modeling system was researched. Using UML (Unified Modeling Language) and the software Rational Rose, the use cases, static logic, dynamic logic and physical deployment of the modeling system were described with the use case diagram, class diagrams, communication diagrams, components diagram and deployment diagram. The research results can guide the development process of the cladding part modeling system with high stability and reliability. DOI: http://dx.doi.org/10.11591/telkomnika.v11i9.3274

Constant Delay Logic Style

A constant delay (CD) logic style is proposed in this paper, targeting at full-custom high-speed applications. The CD characteristic of this logic style regardless of the logic type makes it suitable in implementing complicated logic expressions such as addition. CD logic exhibits a unique characteristic where the output is pre-evaluated before the inputs from the preceding stage is ready. This feature offers performance advantage over static and dynamic domino logic styles in a single-cycle multistage circuit block. Several design considerations including timing window width adjustment and clock distribution are discussed. Using 65-nm general-purpose CMOS technology, the proposed logic demonstrates an average speedup of 94% and 56% over static and dynamic domino logic, respectively, in five different logic gates. Simulation results of 8-bit ripple carry adders show that CD logic is 39% and 23% faster than the static and dynamic-based adders, respectively. CD logic also demonstrates 39% speedup and 64% (22%) energy-delay product (EDP) reduction from static logic at 100% (10%) data activity in 32-bit carry lookahead adders. For 8-bit Wallace tree multiplier, CD logic achieves a similar speedup with at least 50% EDP reduction across all data activities.

Optimal Power Flow Using Adaptive Fuzzy Logic Controllers

This paper presents an approach for optimum reactive power dispatch through the power network with flexible AC transmission systems (FACTSs) devices, using adaptive fuzzy logic controller (AFLC) driven by adaptive fuzzy sets (AFSs). The membership functions of AFLC are optimized based on 2nd-order fuzzy set specifications. The operation of FACTS devices (particularly, static VAR compensator (SVC)) and the setting of their control parameters (QSVC) are optimized dynamically based on the proposed AFLC to enhance the power system stability in addition to their main function of power flow control. The proposed AFLC is compared with a static fuzzy logic controller (SFLC), driven by a fixed fuzzy set (FFS). Simulation studies were carried out and validated on the standard IEEE 30-bus test system.

An 8-GS/s 200-MHz Bandwidth 68-mW $\Delta\Sigma$ DAC in 65-nm CMOS

This brief presents an 8-GS/s 12-bit input ΔΣ digital-to-analog converter (DAC) with 200-MHz bandwidth in 65-nm CMOS. The high sampling rate is achieved by a two-channel interleaved MASH 1-1 digital ΔΣ modulator with 3-bit output, resulting in a highly digital DAC with only seven current cells. The two-channel interleaving allows the use of a single clock for both the logic and the final multiplexing. This requires each channel to operate at half the sampling rate, which is enabled by a high-speed pipelined MASH structure with robust static logic. Measurement results show that the DAC achieves 200-MHz bandwidth, 26-dB SNDR, and -57-dBc IMD3, with a power consumption of 68 mW at 1-V digital and 1.2-V analog supplies. This architecture shows potential for use in transmitter baseband for wideband wireless communication.

Design of 32 kbit one-time programmable memory for microcontroller units

A 32 kbit OTP (one-time programmable) memory for MCUs (micro-controller units) used in remote controllers was designed. This OTP memory is used for program and data storage. It is required to apply 5.5 V to BL (bit-line) and 11 V to WL (word-line) for a OTP cell of 0.35 μm ETOX (EEPROM tunnel oxide) type by MagnaChip. We use 5 V transistors on column data paths to reduce the area of column data paths since they require small areas. In addition, we secure device reliability by using HV (high-voltage) transistors in the WL driver. Furthermore, we change from a static logic to a dynamic logic used for the WL driver in the core circuit. Also, we optimize the WD (write data) switch circuit. Thus, we can implement them with a small-area design. In addition, we implement the address predecoder with a small-area logic circuit. The area of the designed 32 kbit OTP with 5 V and HV devices is 674.725 μm×258.75 μm (=0.1745 mm2) and is 56.3% smaller than that using 3.3 V devices.

TEMPO E REPETIÇÃO NA TEORIA DAS RELAÇÕES INTERNACIONAIS

O presente artigo analisa os conceitos de estrutura do Neo-Realismo e Pós-Estruturalismo das Relações Internacionais. Relacionando tais conceitos com as noções tradicionais e alternativas de tempo, demonstra-se como neo-realistas precisam de categorias temporais não conservadoras para sustentar sua lógica estática, ao passo que o pós-estruturalismo atribui sentido ao "eterno movimento" assumindo noções de tempo tradicionais. Desta forma, pretende-se mostrar como cada abordagem mantém sua coerência interna a partir da adesão tácita à categorias conceituais que lhe são externas.

Resilient and adaptive performance logic

As VLSI technology continues scaling, increasingly significant parametric variations and increasingly prevalent defects present unprecedented challenges to VLSI design at nanometer scale. Specifically, performance variability has hindered performance scaling, while soft errors become an emerging problem for logic computation at recent technology nodes. In this article, we leverage the existing Totally Self-Checking (TSC)/Strongly Fault-Secure (SFS) logic design techniques, and propose Resilient and Adaptive Performance (RAP) logic for maximum adaptive performance and soft error resilience in nanoscale computing. RAP logic clears all timing errors in the absence of external soft errors, albeit at a higher area/power cost compared with Razor logic. Our experimental results further show that dual-rail static (Domino) RAP logic outperforms alternative Delay-Insensitive (DI) code-based static (Domino) RAP logic with less area, higher performance, and lower power consumption for the large test cases, and achieves an average of 2.29(2.41)× performance boost, 2.12(1.91)× layout area, and 2.38(2.34)× power consumption compared with the traditional minimum area static logic based on the Nangate 45-nm open cell library.