Abstract
Due to the intrinsic lack of restoring paths, dynamic logic circuits have significant single-event susceptibility, and thus, they are not preferred in applications requiring high reliability when compared to static logic. However, in high speed applications, this circuit family is still very attractive. This papers presents two layout-based single-event resilient dynamic logic designs. The resultant SET pulse is suppressed because of charge-sharing in the layout-level. Simulation results verify that they enjoy higher single event tolerance. Experimental results validate the fact that approximately 20?~?30 % of magnitude reduction in cross-section is achieved in both designs. On the other hand, the increase in single-event performance is achieved at the expense of power and area overheads of 10 and 15 %, respectively, using our layout style in 130 nm CMOS bulk technology.
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