A novel technique to improve noise immunity of CMOS dynamic logic circuits

Abstract

Dynamic CMOS logic circuits are widely employed in high performance VLSI chips in pursuing very high system performance. However, dynamic circuits are inherently less resistant to noises than static CMOS gates. With the increasing stringent noise requirement due to aggressive technology scaling, the noise tolerance of dynamic circuits has to be first improved for the overall reliable operation of VLSI systems. In this paper, we present a novel noise-tolerant design technique using circuitry exhibiting a negative differential resistance effect. We have demonstrated that using the proposed method the noise tolerance of dynamic logic gates can be improved beyond the level of static CMOS logic gates while the performance advantage of dynamic circuits is still retained.