Spin-transfer Torque Random Access Memory Research Articles

MFM and first order reversal curve (FORC) study of switching mechanism in Co25Pd75 films

Recent research on CoPd alloys with perpendicular magnetic anisotropy has suggested that they might be useful as the pinning layer in CoFeB/MgO-based perpendicular magnetic tunnel junctions for various spintronic applications such as spin-torque transfer random access memory. We have previously studied the effect of seed layer and composition on the structure (by XRD, SEM, AFM, and TEM) and the performance (coercivity) of these CoPd films. These films do not switch coherently, so the coercivity is determined by the details of the switching mechanism, which was not studied in our previous paper. In the present paper, we show that information can be obtained about the switching mechanism from magnetic force microscopy (MFM) together with first order reversal curves, despite the fact that MFM can only be used at the zero field. We find that these films switch by a mechanism of domain nucleation and dendritic growth into a labyrinthine structure, after which the unreversed domains gradually shrink to small dots and then disappear.

Energy minimization in the STT-RAM-based high-capacity last-level caches

Spin-transfer torque random access memory (STT-RAM) is a suitable alternative to DRAM in the large last-level caches (L3Cs) on account of low leakage, the absence of refresh energy and good scalability. However, long latency and high energy consumption for write operations are disadvantages of this technology. The proper utilization of row buffer locality can improve energy efficiency and mitigate negative effects of writing operations in the STT-RAM L3Cs. In this paper, we present an integer linear programming (ILP) formulation which minimizes energy consumption in the STT-RAM-based L3C exploiting the row buffer locality and the prominent features of STT-RAM. Since ILP solvers may not achieve the better result in a reasonable time, we propose a sub-optimal algorithm that obtains the results in a polynomial time. Evaluations demonstrate that on average, our ILP model reduces dynamic energy about 19% and improves row buffer hit rate about 23% compared to the state of the art.

Cache lifetime enhancement technique using hybrid cache-replacement-policy

Driven by the trends of emerging technologies in memories, a non-volatile memory (NVM) has been considered as an alternate technology to replace SRAM in an on-chip cache. Spin-transfer torque random access memory (STT-RAM), a new type of NVM technology has low leakage power and huge density of cells. Besides having advantages, the emerging NVM technologies have limited writes and huge error rates. The write endurance and error rates are influenced by the cache replacement algorithm, which ultimately dictates the lifetime of a cache. Hence, it becomes necessary to develop or modify the cache replacement algorithms for improving the lifetime of the STT-RAM caches. The proposed Hybrid-Cache-Replacement (HCR) policy reduces the impact of the replacement algorithm in such a way that its write endurance improves with reduction in error rate. The incoming data are appropriately placed in the existing block, which have minimum error rates and less number of writes. It has been implemented by comparing the incoming bits with the existing bits in a cache set. The simulation results show that the lifespan of the STT-RAM caches improves by 135%, 165% and 27% along with 2%, 2% and 1% performance overhead when compared to the existing methods.

A Novel Nondestructive Bit-Line Discharging Scheme for Deep Submicrometer STT-RAMs

A combination of semiconductor integrated circuits (IC) and a dense array of scaled magnetic tunnel junctions (MTJ) makes promising Spin-Transfer Torque Random Access Memory (STT-RAM). This emerging memory minimizes the leakage power consumption and provides a high density at scaled technologies. In this paper, we propose a novel non-destructive self-reference sensing scheme for STT-RAM. The proposed technique overcomes the large bit-to-bit variation of MTJ resistance. In the proposed scheme, the stored value in the STT-RAM cell preserves, hence, the long write-back operation is eliminated. Besides, the sensing scheme is accomplished in one step. In this scheme, the Bit-Line is pre-charged and then discharged during read operation. The MTJ resistance state can be found by comparing the time constant of discharging. The simulation results show the overall sensing time is 4 ns when the Bit-Line capacitance is equal to 200 fF.

Proactive correction coset decoding scheme based on SEC-DED code for multibit asymmetric errors in STT-MRAM

As one promising candidate of next generation nonvolatile memory technologies, spin-transfer torque random access memory (STT-MRAM) offers many attractive characteristics, such as high speed, nonvolatility, high integration density, and excellent CMOS process compatibility. However, the performance and reliability of STT-RAM cells are greatly affected by device operating uncertainties and external circuit variation. As a result, write operations of STT-MRAM are not identical, which introduces asymmetric write failure rates for 0→1 and 1→0 bit flipping. Error correcting codes (ECCs) are general solutions for protecting memories from errors. The ECCs most widely used in memory technology are the single error correction and double error detection (SEC-DED) codes. Unfortunately, existing SEC-DED code schemes have limited correction capabilities and do not take the different error rates of memories into consideration. Regarding the failure characteristics (e.g., multibit and asymmetric) of STT-MRAM, conventional SEC-DED codes are not efficiently applicable. In this paper, we propose a proactive correction coset decoding scheme to correct double asymmetric errors for STT-MRAM. The scheme is partitioned into two levels: the proactive correction level (PCL) and the asymmetric correction level (ACL). The PCL proactively handles the single-bit error correction and the ACL analyzes the result from the prior level and corrects the second error. These levels are all based on the same standard coset array. Finally, simulation results with an SEC-DED code show the effectiveness and improvement of the proposed decoding scheme.

Bit-Level Disturbance-Aware Memory Partitioning for Parallel Data Access for MLC STT-RAM

Spin-transfer torque random access memory (STT-RAM) is one of the most promising emerging nonvolatile memory technologies suitable for substituting traditional memory due to its fascinating features, such as high density and low-leakage power. Multilevel cell (MLC) STT-RAM stores two or more bits in a single cell, which can boost data density. Memory partitioning is an efficient method to overcome the impediment of memory bandwidth restricting the speed of parallel data access. However, when applied to previous memory partitioning methods, MLC STT-RAM is still facing challenges. Since these methods have no respect for the issue of read disturbance, the computation performance is unsatisfactory. In this paper, we propose a bit-level disturbance-aware memory partitioning (BaMP) method for parallel data access on MLC STT-RAM. It can effectively eliminate the conflicts between read operations and check operations, which are caused by the read disturbance of STT-RAM, by scheduling the check operations to different time to avoid conflicts. Moreover, bit-level optimization strategies of check merging and check reducing are integrated into the BaMP flow to exploit the MLC STT-RAM structure. The evaluation results on an open data set show that our BaMP outperforms the state-of-the-art method in terms of bank number, storage overhead, performance, and searching speed.

TriZone: A Design of MLC STT-RAM Cache for Combined Performance, Energy, and Reliability Optimizations

Spin-transfer torque random access memory (STT-RAM) is a promising technology for future nonvolatile caches and memories. To increase the storage density, multilevel cell (MLC) technique was recently introduced to STT-RAM designs at the cost of degraded access speed, reliability, and energy efficiency. Existing MLC STT-RAM cache architectures primarily focus on the performance and energy optimizations but ignore the crucial demand for reliability. In this paper, we propose “TriZone”—a holistic design scheme for MLC STT-RAM cache to simultaneously meet the requirements of performance, energy, and reliability. Three cache block configurations, namely hard, soft, and mixed, are constructed with the hard-bit, soft-bit, and both hard-bit and soft-bit of MLC STT-RAM, respectively. By observing the difference of these cache blocks, a nonuniform strength ECC (NUS-ECC) is developed to guarantee the operational reliability of a cache block with a variable decoding delay adapting to the needs of error correction (e.g., the number of the erroneous bits). The whole MLC STT-RAM cache is then partitioned into three regions, each of which is composed of different cache blocks. In order to achieve the best tradeoff among performance, energy, and reliability, we then introduce the dynamic cache partitioning to determine the partition of this tri-way MLC STT-RAM cache according to the runtime characteristic of various applications. Experiment results show that compared with conventional performance-driven MLC STT-RAM cache design with pessimistic ECC, TriZone can improve the system performance and energy by averagely 11.7% (10.0%) and 13.3% (15.7%), respectively, for single-threaded (multiprogram) applications. The additional area overhead associated with NUS-ECC is limited by ~ 3%.

Reuse-Distance-Aware Write-Intensity Prediction of Dataless Entries for Energy-Efficient Hybrid Caches

Emerging nonvolatile memory technologies act as a prominent choice for the larger on-chip caches on account of high density, good scalability, and low static power consumption. However, costly write operations reduce their possibility as a successor of SRAM. To mitigate this problem, a spin-transfer torque random-access memory (STT-RAM)-SRAM hybrid cache architecture is proposed. In such cache architectures, allocation of a write-intensive block is the key challenge for energy efficiency. This paper presents a data allocation policy that reduces the number of writes and energy consumption of the STT-RAM region in the last-level cache by considering the existence of private blocks. Dataless entries are allocated in STT region for such private blocks, and actual data is written only when the block is written back from L1. Heavily written blocks are subsequently migrated to SRAM region. We also present a predictor that helps to redirect the write backs from L1 of dataless entries directly to SRAM region, depending on the predicted reuse-distance-aware write intensity. Experimental evaluation shows that this technique reduces the energy consumption by 34.3% (19.6%) and 23.3% (14.1%), respectively, over two existing techniques in the case of dual (quad) core system.

Write error rates of in-plane spin-transfer-torque random access memory calculated from rare-event enhanced micromagnetic simulations

Stochastic magnetization dynamics at non-zero temperatures gives rise to write errors in spin-transfer-torque random access memory (STTRAM). In this paper, the write error rate (WER) of an in-plane STTRAM bit is estimated by extending a previously developed rare-event-enhancement (REE) technique for spin-transfer-torque switching to an in-plane magnet. Reliable calculation of write error rates up to 10-9 is demonstrated with only ∼103 micromagnetic simulations, thereby making an otherwise prohibitively large computational burden tractable. For the in-plane bit studied here, WERs obtained from the REE-enabled micromagnetic simulations are found to be higher than those obtained within a spatially-coherent (macrospin) switching assumption. Spatially-incoherent switching modes of different types are observed to reduce the switching speed. A detailed study of these spatially-incoherent modes reveals that, at lower applied currents, the end mode controls the WER slope, whereas, at higher applied currents, switching via vortices or anti-vortices governs the WER slope. A sharp change in the WER slope is observed when the latter type of excitation begins to dominate the unswitched population. By further improvements to the REE technique to selectively take into account the vortices and the anti-vortices, reliable prediction of WERs for all ranges of current is demonstrated. The results could help explain prior experimental observations. REE techniques also could be useful for magnetic devices other than STTRAM where rare events remain important and impact device performance.

Progressive Scaled STT-RAM for Approximate Computing in Multimedia Applications

Spintronic memories are one of the most promising candidates as a universal memory. Although they offer superior energy efficiency over the conventional memories, benefiting from approximate computing approach, some novel techniques can be applied to lower the power consumption even further. In this brief, we propose a progressive scaling scheme for spin-transfer torque random access memory (STT-RAM) arrays, by which the power consumption is reduced at the expense of small quality degradation. According to the proposed approach, access transistors in STT-RAM cells are scaled based on an optimized scaling factor, where least significant bits and most significant bits come with different bit error rates in the data word. Simulation results show that the proposed approach provides 36.7% write power dissipation and 25% die area savings, respectively, while negligible quality degradation is observed based on mean structural similarity index.

Performance and Energy-Efficient Design of STT-RAM Last-Level Cache

Recent research has proposed having a die-stacked last-level cache (LLC) to overcome the memory wall. Lately, spin-transfer-torque random access memory (STT-RAM) caches have received attention, since they provide improved energy efficiency compared with DRAM caches. However, recently proposed STT-RAM cache architectures unnecessarily dissipate energy by fetching unneeded cache lines (CLs) into the row buffer (RB). In this paper, we propose a selective read policy for the STT-RAM which fetches those CLs into the RB that are likely to be reused. In addition, we propose a tags-update policy that reduces the number of STT-RAM writebacks. This reduces the number of reads/writes and thereby decreases the energy consumption. To reduce the latency penalty of our selective read policy, we propose the following performance optimizations: 1) an RB tags-bypass policy that reduces STT-RAM access latency; 2) an LLC data cache that stores the CLs that are likely to be used in the near future; 3) an address organization scheme that simultaneously reduces LLC access latency and miss rate; and 4) a tags-to-column mapping policy that improves access parallelism. For evaluation, we implement our proposed architecture in the Zesto simulator and run different combinations of SPEC2006 benchmarks on an eight-core system. We compare our approach with a recently proposed STT-RAM LLC with subarray parallelism support and show that our synergistic policies reduce the average LLC dynamic energy consumption by 75% and improve the system performance by 6.5%. Compared with the state-of-the-art DRAM LLC with subarray parallelism, our architecture reduces the LLC dynamic energy consumption by 82% and improves system performance by 6.8%.

Design Space Exploration for Selector Diode-STTRAM Crossbar Arrays

We report a simulation-based study to understand the integration potential of selector diode (SD) with spin-transfer torque random access memory (STTRAM). SD based on metal–insulator–insulator–metal diode is considered due to features such as high-speed operation, ability to engineer dielectric interfaces and electrode barriers for low $V_{T}$ and bidirectional switching, and immunity to the temperature (due to its tunnel-based conduction). The intended asymmetry in diode $I$ – $V$ behavior provides better sense margin for larger arrays. We describe design challenges and propose device-circuit co-optimization and novel techniques, e.g., write voltage biasing and series/parallel connected SD for robustness and retention. This is the first effort toward solving the design challenges to enable diode-STTRAM crossbar. The proposed structure can enable 3-D stacking of magnetic tunnel junction for densities beyond 4F2.

Temperature dependence of magnetic properties on switching energy in magnetic tunnel junction devices with tilted magnetization

Spin transfer torque random access memory (STT-RAM) based on magnetic tunnel junction (MTJ) is a popular type of memory because of its non-volatility, small size, and nanosecond access time. The temperature effect on the magnetic properties and the initial angle between the free and pinned layer magnetizations in the MTJ cell are significant for the fast switching process in STT-RAM. In this study, the switching energy was investigated with the temperature effect on the magnetic properties at various initial angles. The results show that the saturation magnetization was decreased by increments of the initial temperature, which also resulted in the reduction of the intrinsic critical current density. Consequently, switching energy can be reduced by the increase of both the initial temperature and the initial angle. Although the initial temperature increment in the MTJ cell is interesting for the fast switching process in STT-RAM, the thermal stability factor greater than 40 and the Curie temperature were both considered for the analysis of the switching energy with magnetic properties, for stabilizing the operation of STT-RAM.

Efficient LDPC Code Design for Combating Asymmetric Errors in STT-RAM

Spin-transfer torque random access memory (STT-RAM) is a promising emerging memory technology in the future memory hierarchy. However, its unique reliability challenges, i.e., the asymmetric bit failure mechanism at different bit flippings, have raised significant concerns in its real applications. Recent studies even show that the common memory error repair “remedies” cannot efficiently address them. In this article, we for the first time systematically study the potentials of the strong low-density parity-check (LDPC) code for combating such unique asymmetric errors in both single-level-cell (SLC) and multi-level-cell (MLC) STT-RAM designs. A generic STT-RAM channel model suitable for the SLC/MLC designs, is developed to analytically calibrate all the accumulated asymmetric factors of the write/read operations. The key initial information for LDPC decoding, namely asymmetric log-likelihood ratio (A-LLR), is redesigned and extracted from the proposed channel model, to unleash the LDPC’s asymmetric error correcting capability. LDPC codec is also carefully designed to lower the hardware cost by leveraging the systematic-structured parity check matrix. Then two customized short-length LDPC codes—(585,512) and (683,512)—augmented from the semi-random parity check matrix and the A-LLR based asymmetric decoding, are proposed for SLC and MLC STT-RAM designs, respectively. Experiments show that our proposed LDPC designs can improve the STT-RAM reliability by at least 10 2 (10 4 ) when compared to the existing error correction codes (ECCs) for the SLC (MLC) design, demonstrating the feasibility of LDPC solutions on STT-RAM.

A Full-Sensing-Margin Dual-Reference Sensing Scheme for Deeply-Scaled STT-RAM

Spin transfer torque-random access memory (STT-RAM) has recently been regarded as one of the most promising non-volatile memory candidates for the next-generation computer architectures. However, the readability issue has become a new obstacle for STT-RAM in deeply-scaled technology nodes, owing to (a) the increasing process-voltage-temperature variations but reduced supply voltage, resulting in low sensing margin (SM); (b) reduced current margin between the read current and the critical write current of magnetic tunnel junction, leading to the high read disturbance (RD). Here, to deal with the readability issue of deeply-scaled STT-RAM, we propose a full-sensing-margin dual-reference sensing (FSM-DRS) scheme via exploiting analog signal processing within the sensing circuit design. The proposed FSM-DRS scheme improves SM significantly but with no increase of RD through: (a) including two reference cells which utilize the same structure of the data cells to provide two reference signals, thus reducing the reference mismatch or regularity problem; and (b) adding an analog signal pre-processing operation between the data and reference signals before decision, doubling SM without increasing RD. In comparison with the typical sensing schemes, our simulation results (under the 40 nm technology node) show that our FSM-DRS scheme has an ~70% enhancement in average SM as well as a $\sim 10\times $ decrease in bit error rate.

Read-Tuned STT-RAM and eDRAM Cache Hierarchies for Throughput and Energy Optimization

As capacity and complexity of on-chip cache memory hierarchy increases, the service cost to the critical loads from last level cache (LLC), which are frequently repeated, has become a major concern. The processor may stall for a considerable interval while waiting to access the data stored in the cache blocks in LLC, if there are no independent instructions to execute. To provide accelerated service to the critical loads requests from LLC, this paper concentrates on leveraging the additional capacity offered by replacing SRAM-based L2 with spin-transfer torque random access memory (STT-MRAM) to accommodate frequently accessed cache blocks in exclusive read mode in favor of reducing the overall read service time. Our proposed technique improves the temporal locality while preventing cache thrashing via sufficient accommodation of the frequently read reused fraction of working set that may exhibit distant re-reference interval in L2. Our experimental results show that the proposed technique can reduce the L2 read miss ratio by 51.7% on average compared to conventional STT-MRAM L2 design across PARSEC and SPEC2006 workloads while significantly decreasing the L2 dynamic energy consumption.

Perpendicular STT_RAM cell in 8 nm technology node using Co1/Ni3(1 1 1)||Gr2||Co1/Ni3(1 1 1) structure as magnetic tunnel junction

The perpendicular anisotropy Spin-Transfer Torque Random Access Memory (P-STT-RAM) is considered to be a promising candidate for high-density memories. Many distinct advantages of Perpendicular Magnetic Tunnel Junction (P-MTJ) compared to the conventional in-plane MTJ (I-MTJ) such as lower switching current, circular cell shape that facilitates manufacturability in smaller technology nodes, large thermal stability, smaller cell size, and lower dipole field interaction between adjacent cells make it a promising candidate as a universal memory. However, for small MTJ cell sizes, the perpendicular technology requires new materials with high polarization and low damping factor as well as low resistance area product of a P-MTJ in order to avoid a high write voltage as technology is scaled down. A new graphene-based STT-RAM cell for 8 nm technology node that uses high perpendicular magnetic anisotropy cobalt/nickel (Co/Ni) multilayer as magnetic layers is proposed in this paper. The proposed junction benefits from enough Tunneling Magnetoresistance Ratio (TMR), low resistance area product, low write voltage, and low power consumption that make it suitable for 8 nm technology node.

An energy-efficient 3D-stacked STT-RAM cache architecture for cloud processors: the effect on emerging scale-out workloads

This paper focuses on energy consumption which is a major problem in the dark silicon era. As energy consumption becomes a key issue for operation and maintenance of cloud data centers, cloud computing providers are becoming significantly concerned. Here, we show how spin-transfer torque random access memory (STT-RAM) can be used as an on-chip L2 cache to obtain lower energy compared to conventional L2 caches, like SRAM. High density, fast read access and non-volatility make STT-RAM a significant technology for on-chip memories. Previous studies have mainly studied specific schemes based on common applications and do not provide a thorough analysis of emerging scale-out applications with multiple design options. Here, we discuss different outlooks consisting of performance and energy efficiency in cloud processors by running emerging scale-out workloads. Experiment results on the CloudSuite benchmarks show that the proposed method reduces energy by 51% (on average) and improves energy delay product by 37% (on average) where instruction per cycle degradation is only 22% (on average) compared to the SRAM method.

Nonvolatile Spintronic Memory Array Performance Benchmarking Based on Three-Terminal Memory Cell

For the conventional spin-transfer torque random access memory, tradeoffs exist between read margin and write energy because both read and write currents pass through the same magnetic tunnel junction. To improve the read/write performance and reduce the read disturb rate, three-terminal memory cell structures are investigated and the tradeoffs among read and write performance metrics are explored. A uniform memory array-level benchmarking is performed to compare various spintronic write mechanisms, including spin diffusion, spin Hall effect, domain wall motion, and magnetoelectric (ME) effect. Results show that three-terminal memory cells have the advantage of a small write energy dissipation, and up to two orders of magnitude reduction in the energy-delay product is projected for the domain wall and ME-based memory cells.

State-Transition-Aware Spilling Heuristic for MLC STT-RAM-Based Registers

Multilevel Cell Spin-Transfer Torque Random Access Memory (MLC STT-RAM) is a promising nonvolatile memory technology to build registers for its natural immunity to electromagnetic radiation in rad-hard space environment. Unlike traditional SRAM-based registers, MLC STT-RAM exhibits unbalanced write state transitions due to the fact that the magnetization directions of hard and soft domains cannot be flipped independently. This feature leads to nonuniform costs of write states in terms of latency and energy. However, current SRAM-targeting register allocations do not have a clear understanding of the impact of the different write state-transition costs. As a result, those approaches heuristically select variables to be spilled without considering the spilling priority imposed by MLC STT-RAM. Aiming to address this limitation, this paper proposes a state-transition-aware spilling cost minimization (SSCM) policy, to save power when MLC STT-RAM is employed in register design. Specifically, the spilling cost model is first constructed according to the linear combination of different state-transition frequencies. Directed by the proposed cost model, the compiler picks up spilling candidates to achieve lower power and higher performance. Experimental results show that the proposed SSCM technique can save energy by 19.4% and improve the lifetime by 23.2% of MLC STT-RAM-based register design.