A Full-Sensing-Margin Dual-Reference Sensing Scheme for Deeply-Scaled STT-RAM

Abstract

Spin transfer torque-random access memory (STT-RAM) has recently been regarded as one of the most promising non-volatile memory candidates for the next-generation computer architectures. However, the readability issue has become a new obstacle for STT-RAM in deeply-scaled technology nodes, owing to (a) the increasing process-voltage-temperature variations but reduced supply voltage, resulting in low sensing margin (SM); (b) reduced current margin between the read current and the critical write current of magnetic tunnel junction, leading to the high read disturbance (RD). Here, to deal with the readability issue of deeply-scaled STT-RAM, we propose a full-sensing-margin dual-reference sensing (FSM-DRS) scheme via exploiting analog signal processing within the sensing circuit design. The proposed FSM-DRS scheme improves SM significantly but with no increase of RD through: (a) including two reference cells which utilize the same structure of the data cells to provide two reference signals, thus reducing the reference mismatch or regularity problem; and (b) adding an analog signal pre-processing operation between the data and reference signals before decision, doubling SM without increasing RD. In comparison with the typical sensing schemes, our simulation results (under the 40 nm technology node) show that our FSM-DRS scheme has an ~70% enhancement in average SM as well as a $\sim 10\times $ decrease in bit error rate.