State-Transition-Aware Spilling Heuristic for MLC STT-RAM-Based Registers

Yuanhui Ni,Zhiyao Gong,Chengmo Yang,Keni Qiu,Weiwen Chen

doi:10.1155/2017/1030249

Yuanhui Ni, Zhiyao Gong + Show 3 more

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https://doi.org/10.1155/2017/1030249

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Journal: VLSI Design	Publication Date: Nov 22, 2017
Citations: 2	License type: CC BY 4.0

Affiliation: Capital Normal University, University of Delaware

Abstract

Multilevel Cell Spin-Transfer Torque Random Access Memory (MLC STT-RAM) is a promising nonvolatile memory technology to build registers for its natural immunity to electromagnetic radiation in rad-hard space environment. Unlike traditional SRAM-based registers, MLC STT-RAM exhibits unbalanced write state transitions due to the fact that the magnetization directions of hard and soft domains cannot be flipped independently. This feature leads to nonuniform costs of write states in terms of latency and energy. However, current SRAM-targeting register allocations do not have a clear understanding of the impact of the different write state-transition costs. As a result, those approaches heuristically select variables to be spilled without considering the spilling priority imposed by MLC STT-RAM. Aiming to address this limitation, this paper proposes a state-transition-aware spilling cost minimization (SSCM) policy, to save power when MLC STT-RAM is employed in register design. Specifically, the spilling cost model is first constructed according to the linear combination of different state-transition frequencies. Directed by the proposed cost model, the compiler picks up spilling candidates to achieve lower power and higher performance. Experimental results show that the proposed SSCM technique can save energy by 19.4% and improve the lifetime by 23.2% of MLC STT-RAM-based register design.

Highlights

Electromagnetic radiation effects can cause several types of errors on traditional SRAM-based registers and DRAMbased memory such as single event upset (SEU) and single event functional interrupt (SEFI)
Multilevel cell spin-transfer torque random access memory (RAM) (STT-RAM) (MLC STT-RAM) offers high storage density, and recent studies have shown that the write latency of STT-RAM can be greatly reduced by modifying the bit-cell structure or increasing write current [4]
In order to build a formal spilling cost model, we explore the unbalanced writes to the hard domain and soft domain of multilevel cell (MLC) STT-RAM cells and the exact state-transition cost to identify the spilling cost of each node

Summary

Introduction

Electromagnetic radiation effects can cause several types of errors on traditional SRAM-based registers and DRAMbased memory such as single event upset (SEU) and single event functional interrupt (SEFI). Since write operations involve changing the physical state, NVMs are resilient to radiations in the harsh space environment Among these technologies, STT-RAM has the shortest access policy and can potentially be used to build registers. Among all the emerging NVMs, the spin-transfer torque RAM (STT-RAM) is considered as a promising candidate for on-chip memory because of its advantages, such as low leakage, high density, fast read speed, nonvolatility, and immunity to radiationinduced soft errors [8]. It features much better endurance and performance than other magnetic memory technologies.

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