Abstract
In this work, we study the access (read and write) scheme of the newly proposed Multi-Level Cell Spin-Transfer Torque Random Access Memory (MLC STT-RAM) from both the circuit design and architectural perspectives. Based on the physical principles of the resistance state transition of MLC STT-RAM, we proposed a read circuitry based on Dichotomic search algorithm and three write schemes with various design complexities - simple, complex, and hybrid schemes. The circuit and architectural level evaluations were conducted to analyze the power and performance tradeoffs in each proposed write mechanisms of MLC STT-RAM.
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