Source-drain Electrodes Research Articles

Enabling Hybrid Complementary-TFTs With Inkjet Printed TIPS-Pentacene and Chemical Bath Deposited CdS

We report the fabrication and device analysis to enable high performance/low-temperature complementary thin-film transistors (CTFTs) with 6, 13-Bis(triisopropylsilylethynyl)-pentacene (TIPS-pentacene) and cadmium sulfide (CdS). Isolated transistors are first studied and then integrated in a fully patterned CTFT structure. N-type TFTs were fabricated using atomic layer deposition HfO2 as gate dielectric, followed by a CdS film deposited by chemical bath deposition at 70 °C. A novel approach that uses a parylene-C hard mask to avoid damage to the CdS n-type semiconductor is introduced. Also, a comparison between the n-type transistor performance using two different metals (Au and Al) for source-drain electrodes is presented. P-type transistors were fabricated using a novel approach that combines photolithography and ink-jet printing processes. TIPS-pentacene is deposited with inkjet printing in the active channel well, which is photolithographically defined. The p-type TFT mobilities ranged from 1.2×10-3 to 1.5×10-2 cm2/V-s, whereas for n-type TFTs mobilities were ~ 10 cm2/V-s. CTFTs with a maximum processing temperature of 150 °C are demonstrated. Inverters with gains of 17 were achieved. This fabrication process is compatible with large area and low-cost technologies for flexible electronics applications.

Fabrication of 120-nm-channel-length ferroelectric-gate thin-film transistor by nanoimprint lithography

Nanoimprint lithography (NIL) is one of the most promising device fabrication techniques because it has a high resolution and moderate fabrication cost. Oxide-based thin-film transistors (TFTs) with various physical properties have the potential to outperform Si-based large-scale integration (LSI) devices. In this study, we focus on the miniaturization of oxide-based TFTs by NIL. A ferroelectric-gate thin-film transistor (FGT) was prepared by incorporating a chemical-solution-deposition (CSD)-processed indium tin oxide channel, a Pb(Zr,Ti)O3 (PZT) gate insulator, and sputtered Pt electrodes. The Pt source–drain electrodes and ITO channel were patterned by the NIL process. The results show that we successfully fabricated an FGT with a channel length of 120 nm by NIL. The 120 nm channel length was confirmed by scanning electron microscopy (SEM). The fabricated NIL-FGT showed typical n-channel transistor characteristics. The obtained ON/OFF current ratio, threshold voltage, subthreshold voltage, and field-effect mobility were 103, 0.5 V, 1.0 V/decade, and 0.1–0.2 cm2·V−1·s−1, respectively.

N-channel transparent organic thin-film transistors with Ag/LiF bilayer transparent source–drain electrodes fabricated by thermal evaporation

In this paper, we report the use of Ag/LiF (AL) bilayer transparent source–drain (S/D) electrodes for n-channel F16CuPc-based transparent organic thin-film transistors (OTFTs). The transparent electrodes are deposited at room temperature by thermal evaporation, with devices subsequently fabricated without damaging the active layer or breaking the vacuum. Consequently, we obtain transparent OTFTs based on AL bilayer transparent S/D electrodes with good electron mobility of 1.31 × 10−2 cm−2·V−1·s−1, a high on/off ratio of 4.2 × 106, and an average visible range transmittance of 55.6%.

Semiconducting channel self-imposed in metallic graphene using an oxygen ion reaction

A graphene transistor was simply fabricated by employing ZnO deposition into metallic graphene, for which a source-drain electrode and a semiconductor channel could be formed concurrently. The electric properties of graphene could be adjusted by using ZnO thin film because oxygen was injected into the surface of metallic graphene. The surface oxidation of metallic graphene results in enhanced p-type semiconductor characteristics, especially in an improved on/off current ratio. The degree of the self-imposed semiconducting property is proportional to the degree of oxidation occurring on the graphene surface.

Fabrication of polymer-based transistors with source–drain electrodes made of carbon nanotubes and silver nanoparticles by soft lithography techniques

In this study, we have developed multilayer deposition and patterning processes with a resolution of 1μm that can be used to fabricate all-printed, polymer-based organic field-effect transistors (p-OFETs) on the basis of vacuum-free, solution-processable soft lithography techniques. We have used regioregular poly(3-hexylthiophene) (P3HT) as a soluble polymer semiconductor and poly(methylmethacrylate) as soluble polymer gate insulators. We have compared the electrical properties of p-OFETs with multi-walled carbon nanotubes (MWNTs), silver nanoparticles (NPs), and their composites as printed source–drain (S–D) electrodes in order to fabricate vacuum-free, all-printed p-OFETs. The p-OFETs with MWNT S–D electrodes exhibited higher hole mobility and on/off ratios than the devices with Ag NP S–D electrodes owing to better contact at the MWNT/P3HT interface. The high sheet resistance of MWNT electrodes was considerably reduced by mixing with Ag NPs. Both the contact resistance and channel resistance were maintained at low values, resulting in improved electrical properties of p-OFETs.

A Comparative Investigation of a Pentacene Layer on Gold and PMMA in Bottom-Contact Pentacene Thin Film Transistors

This study demonstrates an attempt to fabricate the 25 µm channel-length bottom-contact pentacene TFTs using thermal evaporation through shadow mask technique and to investigate crystal structure, morphology and electronic structure of the pentacene layer deposited at the same time on gold (Au) source-drain electrodes and Poly(methyl methacrylate) (PMMA) gate-dielectric of the TFTs. The pentacene layers with thicknesses of 50 nm were deposited at the evaporation rates of 0.1, 0.5, 1.0 and 1.5 nm/min at substrate temperatures of 60 °C. These conditions were employed with and without preheating at 80 °C before deposition. Preheating at 80 °C was found to improve quality of the pentacene film on the PMMA gate-dielectric. Using the deposition rate of 1 nm/min and the substrate temperature of 60 °C, best performance of TFTs were obtained. At this deposition condition, pentacene film work function was found to be higher on the Au source-drain electrodes than on the PMMA gate-dielectric.

Unlocking the full potential of light emitting field-effect transistors by engineering charge injection layers

Light emitting field-effect transistors (LEFETs) are a class of next generation devices which combine the switching properties of field-effect transistors (FETs) with light emitting capabilities of organic light-emitting diodes (OLEDs) in a single device architecture. Current LEFET architectures suffer from inefficient charge injection of electrons and holes from the source and drain electrodes, leading to unbalanced charge transport and hence poor device performance. Here we report a simple fabrication method for LEFETs that delivers asymmetric source and drain electrodes comprised of low and high work function materials. The interdigitated low and high work function source–drain electrodes consist of combinations of organic materials, salts, metal oxides and metals. Using this method we were able to obtain a maximum EQE of up to 1.2% in a single layer device with Super Yellow as the active material.

Sensing and Energy Harvesting of Fluidic Flow by InAs Nanowires

Indium arsenide (InAs) nanowire (NW) field effect transistors (FETs) were incorporated into a microfluidic channel to detect the flow rate change as well as to harvest fluid flow energy for electric power generation. Discrete changes in the electric current through InAs NW FETs were observed upon flow rate changes at steps of 1 mL/h (equivalent to ~3 mm/s change in average linear velocity). The current also showed a sign change upon reversing flow direction. By comparing the response of the device with and without a driving voltage between source-drain electrodes, we conclude that the dominant contribution in the response is the streaming potential tuned conductance of NW. In the absence of source-drain voltage, we further demonstrate that the ionic flow could enable generation of an ~mV electrical potential (or ~nA electrical current) inside the InAs NW per mL/h increase of flow rate, most likely due to the charge dragging effect.

Transparent organic thin film transistors with WO3/Ag/WO3 source-drain electrodes fabricated by thermal evaporation

High-performance transparent organic thin film transistors using a WO3/Ag/WO3 (WAW) multilayer as the source and drain electrodes have been developed without breaking the vacuum. The WAW electrodes were deposited by thermal evaporation at room temperature, leading to little damage to organic film. The optimized WAW electrode shows high transmittance (86.57%), low sheet resistance (11 Ω/sq), and a high work function (5.0 eV). Consequently, we obtained high performance devices with mobility of 8.44 × 10−2 cm2/V · s, an on/off ratio of approximately 1.2 × 106, and an average visible range transmittance of 81.5%.

External pressure responsive device based on tunable organic inverter using soft contact lamination

A voltage tunable device which operates by external pressure based on a diode-connected load inverter is successfully fabricated by connecting two transistors adopting bridge-structured polymeric stamps with gold electrodes. When pressure is applied to the polymeric stamp in the drive transistor, the effective channel length between the source–drain electrodes decreases such that the source–drain current is increased and the voltage transfer curves of the inverter are shifted in the positive direction. Thus, a voltage tunable device (or a pressure sensitive inverter) is achieved, because the output voltage of the load inverter comes to have a corresponding relation with the applied pressure. In addition, the sensitivity of this pressure responsive device can be improved by changing the thickness of the polymeric stamp.

Effect of the interlayer for source-drain electrodes on a solution-processed zinc-tin-oxide TFT

An interlayer was introduced between the source and drain (S-D) electrodes and the semiconductor in a solution-processed zinc tin oxide (ZTO) thin-film transistor (TFT). The ZTO TFT with a MoO3 interlayer of 0.5 nm between the ZTO and the S-D electrodes displayed better properties: a mobility of 5.6 cm2/V s, a threshold voltage (Vth) of −1.3 V and a subthreshold slope of 0.9 V/dec with better bias stability and hysteresis. This improvement is attributed to the MoO3’s reduction to a conductor, MoO2, and to the inter-diffusion of the interlayer between the active channel and the S-D layers, as confirmed by the XPS spectra and by a TEM-EDX analysis, respectively.

Fabrication of Polymer-Based Transistors with Carbon Nanotube Source Drain Electrodes Using Softlithography Techniques

In this study, we have developed the multilayer deposition and patterning processes with a resolution of 1 µm for fabricating polymer-based organic field effect transistors (p-OFETs) based on vacuum-free, solution processable softlithography techniques. We have used regioregular poly(3-hexylthiophene) (P3HT) as the soluble polymer semiconductor, and poly(methyl methacrylate) (PMMA) and polyimide as the soluble and insoluble polymer gate insulators, respectively. We have used multiwalled carbon nanotubes (MWNTs) as the printed source–drain (S–D) electrodes in order to fabricate vacuum-free, all printed OFETs. The p-OFETs with MWNT S–D electrodes exhibit higher hole mobility and on/off ratio than the devices with vacuum-evaporated Au electrodes, probably owing to the better contact of the electrode interface and damage-free transfer of electrodes onto the gate insulator. The mobility was further improved by the crystallization of the P3HT film after heat treatment prior to the pattern transfer of P3HT.

P-channel thin-film transistors based on spray-coated Cu2O films

Thin films of cuprous oxide (Cu2O) were grown using solution-based spray pyrolysis in ambient air and incorporated into hole-transporting thin-film transistors. The phase of the oxide was confirmed by X-ray diffraction measurements while the optical band gap of the films was determined to be ∼2.57 eV from optical transmission measurements. Electrical characterization of Cu2O films was performed using bottom-gate, bottom-contact transistors based on SiO2 gate dielectric and gold source-drain electrodes. As-prepared devices show clear p-channel operation with field-effect hole mobilities in the range of 10−4–10−3 cm2 V−1 s−1 with some devices exhibiting values close to 1 × 10−2 cm2 V−1 s−1.

Optimized ink-jet printing condition for stable and reproducible performance of organic thin film transistor

In this work, we fabricated an electrically stable and reproducible organic thin film transistor (OTFT) by optimizing the electrode printing conditions to avoid the coffee ring effect and the Marangoni effect. The electrodes were printed on substrates with different temperature and line spacing to compare the uniformity of electrode morphology and their electrical performance. The Ag gate electrode was printed on poly (methyl methacrylate) (PMMA) coated glass substrate. As a top contact device, source and drain electrodes were also printed on the pentacene layer. The optimized gate electrode was printed at substrate with a temperature of 30°C and 30μm spacing size while the source drain electrodes were printed with 80μm spacing size at 80°C. The final devices showed reproducible electrode morphology and electrical properties with a mobility of 0.025cm2/V-s, threshold voltage Vth=−5.6V and on/off ratio >104.

Gated-Controlled Rectification of a Self-Assembled Monolayer-Based Transistor

A vertical gate symmetrical molecular transistor is demonstrated. It includes self-assembled monolayer of ferrocene molecules chemically bonded to be a flat Au source and Au nanoparticles drain electrodes while gated with the central gate electrode. Using this configuration, we show that negative differential resistance, symmetrical behavior, and rectification effects can be tuned by controlling the gate voltage. The I–V curves shift from symmetric to strongly rectifying over a gate voltage range of a few tenths of volts around a threshold value where the junction behaves symmetrically. This is due to charging of the nanoparticle contact, which modifies the spatial profile of the voltage across the junction, a fact that we have included in a simple theoretical model that explains our experimental results quite well. Our device design affords a new way to fine-tune the rectification of molecular devices in a way that does not necessarily involve the Coulomb charging of the wire.

Transparent Organic Thin Film Transistors Using an Oxide/Metal/Oxide Trilayer as Low-Resistance Transparent Source/Drain Electrodes

This work presents transparent pentacene-based organic thin film transistors (OTFTs) in which an oxide/metal/oxide trilayer provides low-resistance transparent source/drain electrodes. The device structure is glass/indium–tin oxide (ITO)/poly(methyl methacrylate) (PMMA)/pentacene/transparent source–drain electrode. The transparent source/drain electrode consists of a low-resistance metal, silver, that is sandwiched by a high-transmittance oxide, WO3. The structure of the transparent source–drain electrode is optimized by tuning the thickness of each layer. The optimized structure has a sheet resistance of 6.2 Ω/sq. and an optimum transmittance of 70% in the visible wavelength range of 380–780 nm. The pentacene-based OTFT employing optimized transparent source–drain electrode yields an output current (IDS) of -7.08 µA, a field-effect mobility (µ) of 0.22 cm2 V-1 s-1, an on–off drain current ratio of 1.8×105, and a threshold voltage of -15.1 V. OTFTs in which WO3 (5 nm)/Ag (10 nm)/WO3 (30 nm) is used as the source/drain electrode greatly outperform OTFTs in which silver is utilized, because the work function of WO3/Ag/WO3 substantially exceeds that of silver.

Stable Organic Field Effect Transistors with Low-Cost MoO3/Al Source-Drain Electrodes

Stable organic field effect transistors (OFETs) based on copper phthalocyanine (CuPc) are reported using MoO3/Al as source-drain top contacts. By annealing the fabricated device at 130°C in air, the mobility and the stability of the OFETs can be significantly improved in comparison with the untreated device. The heat-treated devices without encapsulation show a device storage stability of nearly 400 h while the untreated one only 183 h. This improvement is suggested to be mainly attributed to the reduction of the contact barrier between CuPc and the electrode, as well as the better alignment of CuPc molecules via post annealing.

Current Enhancement with Contact-Area-Limited Doping for Bottom-Gate, Bottom-Contact Organic Thin-Film Transistors

The current enhancement mechanism in contact-area-limited doping for bottom-gate, bottom-contact (BGBC) p-channel organic thin-film transistors (OTFTs) was investigated both by simulation and experiment. Simulation results suggest that carrier shortage and large potential drop occur in the source-electrode/channel interface region in a conventional BGBC OTFT during operation, which results in a decrease in the effective field-effect mobility. These phenomena are attributed to the low carrier concentration of active semiconductor layers in OTFTs and can be alleviated by contact-area-limited doping, where highly doped layers are prepared over source–drain electrodes. According to two-dimensional current distribution obtained from the device simulation, a current flow from the source electrode to the channel region via highly doped layers is generated in addition to the direct carrier injection from the source electrode to the channel, leading to the enhancement of the drain current and effective field-effect mobility. The expected current enhancement mechanism in contact-area-limited doping was experimentally confirmed in typical α-sexithiophene (α-6T) BGBC thin-film transistors.

Low-voltage flexible pentacene thin film transistors with a solution-processed dielectric and modified copper source–drain electrodes

Low-voltage, flexibility and low-cost are essential prerequisites for large scale application of organic thin film transistors (OTFTs) in future low-end electronics. Here, we demonstrate a low-voltage flexible OTFT by using a low-temperature, solution-processed gate dielectric. Such a dielectric can be well integrated with an Au coated polyimide film, and exhibits a low leakage current density of less than 10−6 A cm−2 and a high capacitance density of 180 nF cm−2. Pentacene films deposited onto the solution-processed dielectric show a highly ordered “thin film phase”. The source–drain (S/D) electrodes are made of in situ modified Cu encapsulated by Au (Au/M-Cu). The obtained flexible OTFT exhibits outstanding electrical characteristics under a gate voltage of only −2 V, which include an on/off ratio of 2 × 104, a mobility (μ) of 1.5 cm2 V−1 s−1, a threshold voltage (VT) of −0.3 V and a subthreshold slope (SS) of 161 mV dec−1. The obtained mobility value is among the highest achieved in flexible pentacene OTFTs. The mechanical flexibility and reliability of the OTFTs are also studied and discussed in detail, and the observed degradation of the device performance under strains is attributed to the damage induced in the electrodes giving rise to increased contact resistance and the phase transition from the thin film phase to bulk phase of the pentacene films.

Simultaneously grown single wall carbon nanotube channel and electrodes in a thin film transistor

Abstract