SOS Devices Research Articles

SOS Device for Women Safety

Women security is need of the hour now-a-days. In India, there are many cases of women harassment and molestation. Safety of women matters let be whether at home, outdoor or it be their work place. The literature surveyed shows that there are many mobile applications that are used for women safety purpose. One recent research study shows that there is a footwear chip which is sticked to the footwear that gets activated when the person taps one leg behind the other 4 times. We focus on developing a prototype that is a smart sos device which gets activated by pressing the button either once or twice. The GPS location is sent to the ICE contacts as soon as the device is turned on. The victim's current location is sent to the ICE contacts. Double press activates device turning on, a Piezo buzzer siren will go out. The buzzer's volume ranges from 80 to 110 dB, and it may be heard 50 feet away. Until the device is turned off it will send the location on the interval of 5 mins and will keep on beeping continuously.

IoT Based Support System

This IoT based support system is an attempt on extending a contribution into lowering the increasing crime rates against children and adults with awareness and technology. The most powerful tool to this race is technology and through it, we want to provide the basic protection and safety assurance to the users. The proposed device/procedures are aimed to provide solution in case of emergencies. The plan is to merge a hardware device with the smartphones that we carry with ourselves daily. The use of the applications of that phone, without physically using it is the focal point of the project. It can be used as an advanced SOS device or a tracking device and can also we developed into a fit band.

SOS and CMOS differential micromagnetodiodes with electrically controlled sensitivity

Essentially new experimental results of two parallel-field differential micromagnetodiodes based on SOS and CMOS technologies with electrically controlled sensitivity are presented. A dramatic increase of the magnetosensitivity by introduction of discontinuous gates in SOS devices, operating in accumulation condition and by forming of additional n +–p junctions in CMOS ones working with extraction mode are achieved. It is shown that the transducer efficiency increases 4.2 and 11.9 times, respectively, in comparison to sensors without gates and collectors. At low frequencies f ≤ 1 kHz, the internal noise of two devices is of 1/ f type. Parasitic effects at f ≤ 35 kHz frequencies of alternating magnetic field are not expected.

Discrimination of osteoporotic patients with quantitative ultrasound using imaging or non-imaging device

Objectives. – Quantitative ultrasound (QUS) has emerged as a new tool in the assessment of fracture risk. The aim of this study was to compare the clinical utility of QUS parameters measured using imaging and non-imaging devices in the discrimination of osteoporotic patients. Methods. – QUS (Broadband Ultrasound Attenuation, BUA dB/MHz, and Speed of Sound, SOS m/s) were measured and then statistical analyses were performed. Results. – The 106 women included were 65 ± 8 years aged. Using DXA, T score was ≤–2.5 at either lumbar spine or hip in 59% of patients, and 25% had osteoporotic fractures. QUS results were different among devices, and these differences were highly dependent on the measured value. There was a similar effect of age and duration of menopause for all parameters. To obtain 90% of sensitivity for the diagnosis of osteoporosis, the thresholds were 50.80 and 71.70 dB/MHz for BUA and 1544.80 and 1551.50 m/s for SOS, using imaging and non-imaging devices, respectively. Belonging to the highest tertile of QUS had a negative predictive value for osteoporosis ranging from 59% to 65%. In the lowest tertile of QUS, the proportion of osteoporotic women was between 73% and 80%. All QUS parameters, except BUA measured with the non-imaging device, were able to discriminate post-menopausal women with fractures after adjustment for age and hip BMD. Conclusions. – Our data suggest that an imaging system improves the utility of BUA measurement, but not SOS, for post-menopausal osteoporosis assessment.

Identification des patientes ostéoporotiques par analyse ultrasonore osseuse avec ou sans imagerie

Objectives: Quantitative ultrasound (QUS) has emerged as a new tool in the assessment of fracture risk. The aim of this study was to compare the clinical utility of QUS parameters measured using an imaging and a non-imaging devices in the discrimination of osteoporotic patients. Methods: QUS (Broadband Ultrasound Attenuation, BUA dB/MHz, and Speed of Sound, SOS m/s) were measured and then statistical analyses were performed. Results: The 106 women included were aged 65 ± 8 years. Using DXA, T score was ≤–2.5 at either lumbar spine or hip in 59% of patients, and 25% had osteoporotic fractures. QUS results were different among devices, and these differences were highly dependent on the measured value. There was a similar effect of age and duration of menopause for all parameters. To obtain 90% of sensitivity for the diagnosis of osteoporosis, the thresholds were 50.80 and 71.70 dB/MHz for BUA and 1544.80 and 1551.50 m/s for SOS, using imaging and non-imaging devices, respectively. Belonging to the highest tertile of QUS had a negative predictive value for osteoporosis ranging from 59% to 65%. In the lowest tertile of QUS, the proportion of osteoporotic women was between 73% and 80%. All QUS parameters, except BUA measured with the non-imaging device, were able to discriminate post menopausal women with fractures after adjustment for age and hip BMD. Conclusions: Our data suggest that an imaging system improves the utility of BUA measurement, but not SOS, for post menopausal osteoporosis assessment.

Requirements for accurate MOS-SOI device simulations

Simulations of the electrical behavior of MOS-SOI devices pose a difficult numerical problem due to the floating substrate region. The numerical analysis techniques required to solve the floating region problem are discussed. Models for the carrier mobilities and lifetime variation with depth into the silicon film are introduced to fit measured SOS device data. The current-voltage characteristics of SOS transistors, including the kink, are accurately simulated and compared to measurements. The floating potential variation with applied gate and drain bias predicted by the simulation is discussed. >

Radiation hardened high performance CMOS VLSI circuit designs

For space or nuclear plant applications, radiation tolerant high performance CMOS VLSI circuit designs, utilising scaled CMOS/SOS technology and scaled bulk CMOS technology, have been reviewed, placing strong emphasis on total dose radiation hardness. Based on radiation induced degradations for conventional CMOS circuits, such as inverters, ring oscillators and memory circuits, total dose radiation hardening technologies have been discussed. Low temperature process and thin oxide introductions are effective for radiation induced threshold voltage shift reduction. Total dose radiation induced field leakage is suppressed by introducing a thin field oxide between the source/drain diffusion layers and a thick field oxide in NMOS transistors, combined with the buried P+ diffusion layer at the P well edge, without sacrificing speed performance. In addition to device/process technologies for total dose radiation hardening, usefulness for NAND logics and static circuits in radiation tolerant CMOS VLSI designs, are shown. Furthermore, radiation tolerance superiority of clocked gate CMOS circuits to transfer gate CMOS circuits in SOS devices, are indicated. Latchup immunity and SEU immunity have also been discussed, for both SOS and bulk devices. Effectiveness of epitaxial substrate and wide transistor introductions for latchup and SEU prevention, is shown, respectively. CMOS/SOS radiation hardened VLSIs and bulk CMOS radiation hardened VLSIs which have been developed by utilising above mentioned technologies, are reported. The entire work described in this paper has made it possible to design radiation hardened high performance VLSI circuits for space or nuclear plant applications, utilising both CMOS/SOS technology and bulk CMOS technology.

Geometric components of charge pumping current in SOS devices

Charge-pumping measurements of the spectral distribution of interface states are performed on three SOS device structures. In contrast to bulk devices with similar channel geometries, there is significant bulk recombination in addition to the normally present interface-state recombination. The bulk recombination produces a sharp upturn in the interface-state density near the bandgap edges. This upturn is an artifact of the analysis method. While it has been observed at both edges of the bandgap, it is usually stronger near the conduction band for n-channel devices and near the valence band for p-channel devices. In the remainder of the bandgap, the interface-state density is accurately measured. Following X-ray exposure, the interface-state density increases, whereas the upturns near the band edges are virtually unchanged. Unlike the case for bulk devices, it is shown that geometric constraints on the motion of majority carriers play an important role in producing recombination at bulk traps. A model is presented that addresses the carrier motion and describes the dependence of the bulk recombination on the channel geometry.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A comparison of fine-dimension silicon-on-sapphire and bulk-silicon complementary MOS devices and circuits

The fabrication of fine-dimension silicon-gate MOS devices on both silicon-on-sapphire and bulk-silicon substrates has made possible a direct comparison of the electrical characteristics of devices based on these technologies. The same CMOS test chip design was used in both cases and provided both n- and p-channel devices having gate dimensions ranging down to submicrometer levels. Extensive electrical evaluation of the resulting devices has enabled quantitative comparison of carrier mobilities, short- and narrow-channel threshold voltage shifts, punchthrough, and subthreshold characteristics for SOS and bulk-silicon technologies. The effect of epitaxial film thickness on these properties for SOS devices is also discussed. An anomalous narrow-channel threshold voltage shift effect is observed in SOS devices and explained in terms of parasitic device characteristics. The general conclusion based on the observations made is that short-and narow-channel effects in SOS devices are significantly less of a problem than in bulk silicon devices at these gate dimensions. The direct comparison of the dynamic performance of SOS and bulk CMOS circuits can be obscured, for example by differences in gate oxide thickness and threshold voltages. In this case, however, both gate oxide thickness and threshold voltages have been closely matched. This, together with the fact that the circuits were fabricated by the same processing facility using the same chip design, should increase the reliability of any comparison. The results have indicated that at 1-µm dimensions the propagation delay of SOS CMOS circuits is 60 percent lower than that of equivalent bulk-silicon CMOS circuits.

Dielectric integrity of the gate oxide in SOS devices : R. K. Smeltzer and C. W. Benyon, Jr.RCA Rev.45, 194 (1984)

This paper presents a new method of forming a Si/SiGe dual channel on a Si0.8Ge0.2 virtual substrate. Generally, in a CMOS process using a Si/SiGe dual channel, due to several processes involving ion-implantation, annealing and dry-etching after the deposition of the Si/SiGe dual channel, the surface can be damaged, leading to reduced electrical properties. However, if the dual channel is formed during a specific stage of the CMOS process, the defects of the dual channel can be reduced and the thermal stability will be excellent. Therefore, in this paper, a method for minimizing the defects of the dual channel is presented. This method uses the segregation of the Ge in the oxidation process of a SiGe. A Si/SiGe dual channel formed using this method achieved results that were identical to a dual channel deposited using the chemical vapor deposition (CVD) method.

A subnanosecond 8K-gate CMOS/SOS gate array

An 8370-gate CMOS/SOS gate array has been developed using a Si-gate CMOS/SOS process with two-level metallization. The gate lengths of the transistors are 1.8 and 1.9 /spl mu/m for the n-channel and p-channel, respectively. Subnanosecond typical gate delay times have been obtained. Typical delay times of inverter, two-input NAND, and two-input NOR gates are 0.67, 0.87, and 0.99 ns, respectively, under a typical loading condition (three fan outs and 2 mm first metal). It is shown that ECL speed with CMOS power can be achieved in a system by using the CMOS/SOS gate array. Advantages of the SOS device on speed performance are also discussed.

Analysis of leakage currents in CMOS/SOS devices

Understanding the origin and mechanism of leakage currents in CMOS/SOS transistors constitutes an important step towards the advancement of SOS technology for VLSI applications. In this letter, the bias and geometrical dependence of both n- and p-channel transistors has been analysed in detail. These variations have been correlated with independent lifetime measurements, which indicate that both bulk generation and back surface inversion play important roles in controlling leakage in SOS devices.

The design and performance of near micron SOS MOSFETs

SOS MOSFETs with excellent high speed operation capability (>1GHz) have been designed using computer aided process design techniques and fabricated using state of the art processing technology. The process was optimised for 0.8 to 1.0μm channel length SOS devices. The subthreshold current slope of these devices pushes the theoretical limit at 60 millivolts per decade of current which is further evidenced by ring oscillator single stage delays as low as 85 picoseconds. The leakage current of these devices ranged from 1 to 20 picoamps at 1.0μm channel length as the channel width decreased from 10 to 2μm. Additional data is presented on the channel length and width dependence of the threshold voltage, source-drain breakdown voltage, effective channel mobility, and subthreshold current slope.

Improvement of SOS Device Performance by Solid-Phase Epitaxy

Crystalline quality in the whole region of silicon film on sapphire substrate has been improved by doubly applying solid-phase epitaxial regrowth combined with amorphization of both the silicon surface and the silicon-sapphire interface regions of SOS. Observations, by Rutherford backscattering and chemical delineation, indicate that planar defect density in the film becomes less than 1/100 of that in an as-grown film. Effective mobilities of n- and p-channel FETs in the improved film are 520 and 225 cm2/V·s, which are 1.3 times and 1.1 times larger than those in the as-grown film, respectively. A significantly reduced drain leakage current of 1.8×1012 A/50 µm for n-channel FET is obtained, whose value is about 1/100 of those in as-grown samples. The higher mobility and lower leakage current thus obtained, should be attributed to the drastic improvement of crystalline quality in the whole region of SOS by the double solid-phase epitaxy.

Non-uniformities in ultra-thin oxide layers and their effect on the properties of tunnel MOS, MOM, and SOS devices

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Effect of lifetime on SOS capacitance measurements

For SOS devices, the capacitance-voltage curves at various frequencies differ dramatically between MOS capacitors with and without a sidewall. This is explained in terms of the increase in minority carrier generation rate as the silicon-sapphire interface is approached. In some cases, this property facilitates the determination of the threshold voltage of the parasitic sidewall capacitor.

Improvement in gate breakdown voltage for SOS devices

It was attempted to improve low gate breakdown voltage for an air-isolated SOS devices, employing ion-beam etching technology for silicon-island formation. Gate breakdown origin was clarified with SEM observation. As a result, it has been found that 1) low gate breakdown voltage for air-isolated SOS devices is caused by thinner gate oxide at the bottom of a steep silicon-island edge, and 2) ion-beam etching with the ion-beam incident angle over 40° allows the silicon island to have a sidewall angle under 35°, thus resulting in uniform gate oxide thickness. Consequently, the gate breakdown voltage for the air-isolated SOS devices can be improved to as high as that for dielectric isolated SOS devices.

Recent results of high magnetic field experiments on MOSFETS in Grenoble

A brief review is given about recent work on silicon inversion layers at the high magnetic field facility in Grenoble. Shubnikov-De Haas oscillations in SOS devices in fields up to 20 Tesla showed a beating effect which presumably arises from anisotropic internal stress. Cyclotron resonance experiments under uniaxial pressure on (100) MOSFETs revealed the occupation of the higher subband system with increasing pressure, which did not show-up in SdH oscillations. In (111) devices with 6-fold valley degeneracy structure has been observed in the SdH effect at high magnetic fields around 20 Tesla, which is interpreted as valley splitting. New data are reported about energy losses of electrons and holes in the non-ohmic regime.

Recent results of high magnetic field experiments on mosfets in Grenoble

Abstract A brief review is given about recent work on silicon inversion layers at the high magnetic field facility in Grenoble. Shubnikov-De Haas oscillations in SOS devices in fields up to 20 Tesla showed a beating effect which presumably arises from anisotropic internal stress. Cyclotron resonance experiments under uniaxial pressure on (100) MOSFETs revealed the occupation of the higher subband system with increasing pressure, which did not show-up in SdH oscillations. In (111) devices with 6-fold valley degeneracy structure has been observed in the SdH effect at high magnetic fields around 20 Tesla, which is interpreted as valley splitting. New data are reported about energy losses of electrons and holes in the non-ohmic regime.

A new buried-oxide isolation for high-speed high-density MOS integrated circuits

The BO-MOS has an extensive oxide-isolated structure which isolates not only the sidewall but also the bottom of the source and drain diffusions, similar to SOS-MOS, and yet it retains high carrier mobility and low-leakage junction properties. A 1024-bit static NMOS RAM is successfully fabricated using photomasks of a redesigned high-density bulk NMOS RAM (Fujitsu MBM8115). The ring oscillator circuit fabricated using existing SOS-CMOS photomasks shows an equivalent speed-power performance to the original SOS device. The fabrication sequence for the BO-MOS requires the same number of photomasks as for the conventional MOS devices.