Radiation hardened high performance CMOS VLSI circuit designs

Abstract

For space or nuclear plant applications, radiation tolerant high performance CMOS VLSI circuit designs, utilising scaled CMOS/SOS technology and scaled bulk CMOS technology, have been reviewed, placing strong emphasis on total dose radiation hardness. Based on radiation induced degradations for conventional CMOS circuits, such as inverters, ring oscillators and memory circuits, total dose radiation hardening technologies have been discussed. Low temperature process and thin oxide introductions are effective for radiation induced threshold voltage shift reduction. Total dose radiation induced field leakage is suppressed by introducing a thin field oxide between the source/drain diffusion layers and a thick field oxide in NMOS transistors, combined with the buried P+ diffusion layer at the P well edge, without sacrificing speed performance. In addition to device/process technologies for total dose radiation hardening, usefulness for NAND logics and static circuits in radiation tolerant CMOS VLSI designs, are shown. Furthermore, radiation tolerance superiority of clocked gate CMOS circuits to transfer gate CMOS circuits in SOS devices, are indicated. Latchup immunity and SEU immunity have also been discussed, for both SOS and bulk devices. Effectiveness of epitaxial substrate and wide transistor introductions for latchup and SEU prevention, is shown, respectively. CMOS/SOS radiation hardened VLSIs and bulk CMOS radiation hardened VLSIs which have been developed by utilising above mentioned technologies, are reported. The entire work described in this paper has made it possible to design radiation hardened high performance VLSI circuits for space or nuclear plant applications, utilising both CMOS/SOS technology and bulk CMOS technology.