Dielectric integrity of the gate oxide in SOS devices : R. K. Smeltzer and C. W. Benyon, Jr.RCA Rev.45, 194 (1984)

Abstract

This paper presents a new method of forming a Si/SiGe dual channel on a Si0.8Ge0.2 virtual substrate. Generally, in a CMOS process using a Si/SiGe dual channel, due to several processes involving ion-implantation, annealing and dry-etching after the deposition of the Si/SiGe dual channel, the surface can be damaged, leading to reduced electrical properties. However, if the dual channel is formed during a specific stage of the CMOS process, the defects of the dual channel can be reduced and the thermal stability will be excellent. Therefore, in this paper, a method for minimizing the defects of the dual channel is presented. This method uses the segregation of the Ge in the oxidation process of a SiGe. A Si/SiGe dual channel formed using this method achieved results that were identical to a dual channel deposited using the chemical vapor deposition (CVD) method.