Soft Error Rate Research Articles

Frequency dependence of soft error rates induced by alpha-particle and heavy ion

Frequency dependence of soft error rates induced by alpha-particle and heavy ion

Efficient Modeling of Single Event Transient Effect with Limited Peak Current: Implications for Logic Circuits.

The problem that the conventional double-exponential transient current model (DE model) can overdrive the circuit, which leads to the overestimation of the soft error rate of the logic cell, is solved. Our work uses a new and accurate model for predicting the soft error rate that brings the soft error rate closer to the actual. The piecewise double-exponential transient current model (PDE model) is chosen, and the accuracy of the model is reflected using the Layout Awareness Single Event Multi Transients Soft Error Rate Calculation tool (LA-SEMT-SER tool). The model can characterize transient current pulses piecewise and limit the peak current magnitude to not exceed the conduction current. TCAD models are constructed from 28 nm process library and cell layouts. The transfer characteristic curves of devices are calibrated, and functional timing verification is performed to ensure the accuracy of the TCAD model. The experimental results show that the PDE model is not only more consistent with TCAD simulation than the DE model in modeling the single event transient currents of the device, but also that the SER calculated by the LA-SEMT-SER tool based on the PDE model has a smaller error than the SER calculated by the LA-SEMT-SER tool based on the DE model.

Enhanced Soft Error Rate Estimation Technique for Aerospace Electronics Safety Design via Emulation Fault Injection

In this paper, we propose Automatic Configuration Memory Fault Injection (ACMFI), a tool that calculates the architectural vulnerability factor (AVF) and soft error rate (SER) using the emulation fault injection technique. SER, which is essential for the safety design of aerospace electronics, can be obtained by experiments (beam tests) performed in a beam facility equipped with high-energy radiation facilities. However, SER calculation using beam tests has the disadvantage of a high cost and a long waiting time, making it difficult to use in the conceptual design stage, which is the aerospace system development stage and the initial HW/SW development stage. Using the emulation fault injection method, it is possible to estimate the SER, which can be used in the system safety design phase. This paper describes the ACMFI tool, which automatically performs emulation fault injection in SRAM-based FPGAs, which are widely used in aerospace electronic hardware. Unlike the existing methods, the proposed method has the advantage of minimizing the side effects by injecting faults into a dedicated SRAM area. In other words, the SER obtained by the proposed method can be estimated more accurately than the SER result obtained by the existing method. To prove the accuracy of the proposed test method, the SER calculated by performing an emulation fault injection test on the same FPGA was compared with the SER results tested at the beam facility. The method of obtaining SER using the proposed ACMFI gave results that were closer to the SER obtained by testing at the beam facility than the method of obtaining SER using the existing EMFI. The proposed method is used to calculate the failure rate, which is a key variable in determining the development assurance level when performing safety design tests in aerospace system development, enabling the development of safer systems and lower cost/higher quality aerospace electronic equipment than before.

Fault tolerance evaluation study of a RISC-V microprocessor for HEP applications

The utilization of a radiation-hard microprocessor or a System-on-Chip (SoC) design methodology significantly benefits the future design of ASICs for HEP experiments. To evaluate the fault tolerance of a radiation-hard design, it is important to obtain detailed information on the soft error rate and contributing factors. This article presents a simulation-based approach to investigate the effects of faults induced by single event transients in a microprocessor based on the open RISC-V instruction set architecture.

Contribution of Secondary Alpha Particles to Soft Error Rates in Space Systems

Contribution of Secondary Alpha Particles to Soft Error Rates in Space Systems

An Improved Model of Single-Event Transients Based on Effective Space Charge for Metal-Oxide-Semiconductor Field-Effect Transistor.

In this paper, a single-event transient model based on the effective space charge for MOSFETs is proposed. The physical process of deposited and moving charges is analyzed in detail. The influence of deposited charges on the electric field in the depletion region is investigated. The electric field decreases in a short time period due to the neutralization of the space charge. After that, the electric field increases first and then decreases when the deposited charge is moved out. The movement of the deposited charge in the body mainly occurs through ambipolar diffusion because of its high-density electrons and holes. The derivation of the variation in electric field in the depletion region is modeled in the physical process according to the analysis. In combination with the ambipolar diffusion model of excessive charge in the body, a physics-based model is built to describe the current pulse in the drain terminal. The proposed model takes into account the influence of multiple factors, like linear-energy transfer (LET), drain bias, and the doping concentration of the well. The model results are validated with the simulation results from TCAD. Through calculation, the root-mean-square error (RMSE) between the simulation and model is less than 3.7 × 10-4, which means that the model matches well with the TCAD results. Moreover, a CMOS inverter is simulated using TCAD and SPICE to validate the applicability of the proposed model in a circuit-level simulation. The proposed model captures the variation in net voltage in the inverter. The simulation result obviously shows the current plateau effect, while the relative error of the pulse width is 23.5%, much better than that in the classic model. In comparison with the classic model, the proposed model provides an RMSE of 7.59 × 10-5 for the output current curve and an RMSE of 0.158 for the output voltage curve, which are significantly better than those of the classic model. In the meantime, the proposed model does not produce extra simulation time compared with the classic double exponential model. So, the model has potential for application to flow estimation of the soft error rate (SER) at the circuit level to improve the accuracy of the results.

A Total Self Checking Comparator Implementable on FPGAS Using Bist Technology

an integrated circuits (IC) "manufacturing tests" may be made easier to administer with the use of design for testability (DFT). Integrated circuits' embedded memory tests make use of the TSC (TSC) approach. We have shown the TSC method and several algorithms used in TSC for the purpose of testing embedded memory in this article. An address generator, controller, comparator, and memory are the four main components of this kind of memory TSC technology. This paper details the three memory TSC controller implementation techniques. The memory TSC controller is modelled in Verilog HDL, and its accuracy is checked using the RTL compiler before synthesis.
 Here we provide a way to build TSC comparators for TSC systems that may be implemented on FPGAs—totally self-checking (TSC) systems—that can be used online. By directly measuring the output of each lookup table (LUT), this approach may be utilised to do comprehensive online diagnostics of all LUTs. This entails mapping the basic components of the comparator with a limited number of test patterns. With our technique, we can achieve exhaustive diagnosis with a small number of test patterns on the order of n [O(n)] (where n is the input number to the comparator) while yet covering all bases 100% of the time, even if we are just aware of the LUT's specs and not its exact structure. For systems that need absolute reliability, FPGAs will be a perfect fit. Our experiment also included a single-event upset (SEU) induced by neutron radiation to validate the soft error rate (SER) in a field-programmable gate array (FPGA) based on static random-access memory (SRAM).

Influence of 0.1–10 MeV neutron-induced SEUs on estimation of terrestrial SER in a nano-scale SRAM

The impact of 0.1–10 MeV neutron-induced single-event upsets (NSEUs) on terrestrial SER (soft error rate) prediction is analyzed for several broad spectrum neutron sources based on 0.1–200 MeV NSEU energetic-dependent cross-sectional data of a 40 nm SRAM. The results show that for test facilities with abundant <10 MeV neutrons, such as ISIS ChipIR, J-PARC BL10, CSNS Back-n, and CSNS BL09, the terrestrial SER is overestimated. The overestimation could reach 78%–287%. By reducing the cutoff energy (Emin) from 10 to 6 MeV, the overestimation can be decreased. However, the overestimation can still reach up to 164% in this case, significantly larger than the results reported by previous studies. By analyzing the contribution of neutrons in different energy bins to NSEUs, the discrepancy is proved to be attributed to the sensitivity of NSEUs to 0.1–1 MeV neutrons, along with the overpopulation of 0.1–1 MeV neutrons for certain test facilities, such as ISIS ChipIR and CSNS BL09. Therefore, it is necessary to take 0.1–1 MeV NSEU sensitivity into account when studying the prediction method using broad spectrum neutron sources.

New insights into diffusion–collection modeling of radiation-induced charge in semiconductor devices

Charge diffusion from an ion track and its collection by a biased contact in a semiconductor domain is modeled and analyzed within the framework of the so-called diffusion–collection approach. We successively examine the case of charge diffusion from a point source and from a linear distribution, introducing and discussing the concept of collection velocity at the point where the collection current is evaluated. Analytical formulations of the collected charge, collection current, and collection velocity are developed. Implications for the calculation of the soft error rate in complementary metal-oxide-semiconductor circuits exposed to ionizing particles are derived. Finally, our model provides new insights into the correct definition of the charge collection velocity in collection–diffusion models.

Novel radiation-hardened-by-design (RHBD) 14T memory cell for aerospace applications in 65 nm CMOS technology

With the reduction of MOS transistor process size, the ability of static random access memory (SRAM) to resist single event upset plays an important role in reducing the soft error rate of chips. In this paper, a novel Radiation Hardened By Design Cell (RHBD-14T) using source isolation technology to reduce the number of sensitive nodes is proposed, compared with the following latest radiation-hardened memory cells (WE-Quatro, RHPD-12T, SAR-14T, SEA-14T, QUCCE-12T, SARP-12T, EDP-12T, QCCS, SCCS and SERSC-16T), the proposed RHBD-14T saves 0.5%, −5.3%, 100.2%, 83.6%, −18.5%, −22.8%, 83.7%, 72%, −2.1%, 171% of read-delay time and −13.4%, −36.3%, −34.4%, 24.1%, 8.4%, 153.1%, 47.8%, 14.7%, −2.8%, −32.8% of write delay time, respectively. In addition, RHBD-14T has the smallest power consumption and the largest hold static noise margin (HSNM), read static noise margin (RSNM) and charge-SNM to power-area-delay (QSPAD), which means it is more suitable for radiation intensive space environment.

Soft Error Simulation of Near-Threshold SRAM Design for Nanosatellite Applications

This paper presents the benefit of the near-threshold design of random-access memory (SRAM) design to reduce software errors during very low-power operations in nanosatellites. The near-threshold design is based on an optimization of the use of the Schmitt trigger structure for a 45 nm technology. The results of the soft error susceptibility of the optimized design are compared to a standard 6T SRAM cell. These two designs are modeled and validated by comparing the results with experimental measurements of both static noise margin (SNM) and single event upset (SEU). The optimized circuit reduces the multiple upsets occurrence from 95% down to 14%. Based on the use of simulation tools, the paper demonstrates that the near-threshold design of SRAM is an excellent candidate for the radiation point of view for agile nanosatellites. The results computed for the near-threshold SRAM device demonstrate an improvement of a factor of up to 25 of the soft error rate (SER) in a GEO orbit.

Impact of CnRx Structure on Soft Error Rates of Flip-Flop Designs at 22-nm FD SOI Node

Embedded Silicon Germanium (eSiGe) is used in the channel region of PFET devices at the 22-nm FD SOI node. The use of eSiGe results in channel regions becoming strained, which results in better hole mobility and increased performance. However, if the active diffusion regions are too short on each side of a PFET gate, then the effect of channel strain is reduced, and performance is reduced. The Continuous Active Diffusion (CnRx) layout construct suggested by the foundry is a way to help keep channel strain present within a single cell design. In this paper the CnRx construct is implemented in a 22-nm FD SOI test chip and soft error rates of stacked-transistor flip-flops are shown to increase with heavy ion irradiation. The effect of channel strain on PFETs results in higher collected charges from ion strikes, and charges are more easily passed between adjacent transistors through strained channels. However, with careful schematic and layout design, these effects can be mitigated to produce both high performance and radiation tolerant cells using the CnRx construct.

Understanding the Link Between Complex Digital Devices Soft Error Rate and the Running Software

Understanding the Link Between Complex Digital Devices Soft Error Rate and the Running Software

An Analysis of the Significance of the 14N(n, p) 14C Reaction for Single-Event Upsets Induced by Thermal Neutrons in SRAMs

The thermal neutron threat to the reliability of electronic devices caused by <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">10</sup> B capture is a recognized issue that prompted changes in the manufacturing process of electronic devices with the aim of limiting as much as possible the presence of this isotope nearby device sensitive volumes. <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">14</sup> N can also capture thermal neutrons and release low-energy protons (through the <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">14</sup> N(n,p) <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">14</sup> C reaction) that have high enough linear energy transfer to cause single-event upsets (SEU). Typically, nitrogen is used in thin barrier layers made of TaN or TiN or even as insulator in the form of Si <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sub> . Numerical simulations on sensitive volumes calibrated on proton and ion experimental data and with an accurate description of the metallization layer on top of the sensitive region show that the presence of nitrogen in these thin barrier layers can be enough to justify the experimentally observed thermal neutron SEU cross section for a static random access memory sensitive to low-energy protons. Nevertheless, the expected SEU cross section from thermal neutrons is usually a few orders of magnitude lower than that of high-energy particles, therefore, not representing an important threat in atmospheric applications. At the same time, for high-energy accelerators, the contribution to the total soft error rate could become substantial, though easy to handle by margins.

SECDED code and its extended applications in DRAM system

SECDED code is the combinational logic for communication of data between microprocessors and memories which is commonly used in semiconductor systems due to its advantage in implementation. With advances in semiconductor integrated circuit technology, the soft error rate and importance of selecting optimal codes increase. This paper presents SECDED codes and their major expansion theoretical application and gives suggestions for optimization needs.

Physics-Based Analytical Formulation of the Soft Error Rate in CMOS Circuits

The exponential dependence of the soft-error rate (SER) with critical charge in CMOS circuits, empirically proposed by Hazucha and Svensson, is derived in the framework of the diffusion-collection approach. A full analytical formulation is established, linking the SER with physical and technological parameters, notably the circuit supply voltage, carrier diffusion coefficient and ion characteristics.

A 30 MeV-cyclotron-based quasi-monoenergetic neutron source

This study developed a quasi-monoenergetic neutron source (QMN) for the semiconductor device's soft error rate test (SER). Quasi-monoenergetic neutrons are generated by Be(p,n)B99 nuclear reaction with a 1 mm beryllium target and 30 MeV protons from a cyclotron. An 8 mm water in the back of the beryllium target is used for avoiding proton penetration. The neutron spectra simulated by MCNP showed that the peak energy was around 26.5 MeV. The heat flow and mechanical properties are numerically analyzed, and the safe operating conditions are therefore determined.

Experimental study on real-time measurement of single-event effects of 14 nm FinFET and 28 nm planar CMOS SRAMs based on Qinghai-Tibet Plateau

Based on the Yangbajing International Cosmic Ray Observatory in Lhasa with an altitude of 4300 m, a long-term real-time experiment is carried out in order to measure the atmospheric radiation induced soft errors in 14 nm FinFET and 28 nm planar CMOS SRAM array. The underlying mechanisms are also revealed. Five boards are used in the test, four of which are equipped with 28-nm process devices, and one board is equipped with 14-nm process devices. After removing the unstable bad bits, the actual effective test capacity is 7.1 Gb. During the test, the on-board FPGA reads the stored contents of all the tested devices in real time, reports the error information (occurrence time, board number, column number, device number, error address, error data) and corrects the error. The duration of the test is 6651 h. A total of 56 single event upset (SEU) events are observed, they being 24 single bit upset (SBU) events and 32 Multiple Cell Upset (MCU) events. Based on previous results of 65-nm SRAM, the study finds that SER continues to decrease with the reduction of process size, but the proportion of MCU in 28-nm process devices (57%) exceeds SBU, which is a process “maximum point” of MCU sensitivity, and the maximum size of MCU is 16 bits. Although the Fin spacing of the 14-nm FinFET device is only about 35 nm, and the critical charge decreases to sub-fC, the introduction of the FinFET structure leads to the change of charge collection and the sensitive volume sharing mechanism , and the shallow trench isolation leads to the narrowing of the charge diffusion channel. On the other hand, the surface area of the sensitive volume decreases to 0.0024 μm&lt;sup&gt;2&lt;/sup&gt;, resulting in a significant decrease in the soft error rate of both SBU and MCU in the 14-nm process.

An Analytical Approach to Calculate Soft Error Rate Induced by Atmospheric Neutrons

In the atmosphere, it is generally understood that neutrons are the main contributor to the soft error rate (SER) in electronic devices. These particles are indeed able to trigger nuclear reactions in the sensitive regions of the devices, leading to secondary ions that may ionize the matter sufficiently to upset a memory cell or induce a transient signal, known as soft errors. For reliability purposes, it is crucial to be able to estimate the SER associated with a given technology, which is typically characterized by its sensitive volume and its threshold linear energy transfer (LET). As an alternative to the usual Monte Carlo methods, in this work we present an analytical model for SER prediction, where we separate the radiation–matter interaction from the geometry considerations (sensitive volume). By doing so, we show that the SER can be expressed as the sum of two contributions that can be calculated for any threshold LET and any sensitive volume size. We compare our proposed approach to existing Monte Carlo simulations in the literature, obtaining a very good agreement despite our approximations, thus validating our approach. As an additional result, we can show that, for future down-sized technologies that may be more sensitive to radiation effects, the contribution of neutrons in the 1–10 MeV energy range to the SER is expected to decrease.

Analysis of Single Event Transient Effects in Standard Delay Cells Based on Decoupling Capacitors

Single Event Transients (SETs), i.e., voltage glitches induced in combinational logic as a result of the passage of energetic particles, represent an increasingly critical reliability threat for modern complementary metal oxide semiconductor (CMOS) integrated circuits (ICs) employed in space missions. In rad-hard ICs implemented with standard digital cells, special design techniques should be applied to reduce the Soft Error Rate (SER) due to SETs. To this end, it is essential to consider the SET robustness of individual standard cells. Among the wide range of logic cells available in standard cell libraries, the standard delay cells (SDCs) implemented with the skew-sized inverters are exceptionally vulnerable to SETs. Namely, the SET pulses induced in these cells may be hundreds of picoseconds longer than those in other standard cells. In this work, an alternative design of a SDC based on two inverters and two decoupling capacitors is introduced. Electrical simulations have shown that the propagation delay and SET robustness of the proposed delay cell are strongly influenced by the transistor sizes and supply voltage, while the impact of temperature is moderate. The proposed design is more tolerant to SETs than the SDCs with skew-sized inverters, and occupies less area compared to the hardening configurations based on partial and complete duplication. Due to the low transistor count (only six transistors), the proposed delay cell could also be used as a SET filter.