Abstract
The utilization of a radiation-hard microprocessor or a System-on-Chip (SoC) design methodology significantly benefits the future design of ASICs for HEP experiments. To evaluate the fault tolerance of a radiation-hard design, it is important to obtain detailed information on the soft error rate and contributing factors. This article presents a simulation-based approach to investigate the effects of faults induced by single event transients in a microprocessor based on the open RISC-V instruction set architecture.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
