SoC Design Research Articles

Techno-Economic Optimization of SOC Design and Operating Conditions in a Solid Oxide Fuel Cell-Gas Turbine Hybrid System

Solid oxide fuel cell-gas turbine (SOFC-GT) hybrid systems can reach exceptionally high fuel-to-electricity conversion efficiencies while emitting virtually zero criteria pollutants. Due to these characteristics and their fuel-flexibility, SOFC-GT hybrid systems are seen as a key technology in sustainable power generation. In this work we explore SOFC cell design parameters that can synergistically reduce thermal stress and cost, as well as system-level design strategies to maximize economic performance. Results show that NG-fueled hybrid systems can reach efficiencies of 75%-LHV at a cost-of-electricity of 77.73 $/MWh. A similar biogas system with integrated anaerobic digester and biogas upgrading resulted in an efficiency of 53%-LHV and a cost-of-electricity of 137.19 $/MWh.

Accelerating GRAPPA reconstruction using SoC design for real-time cardiac MRI

Real-time cardiac MRI is a rapidly developing area of research that has the potential to improve the diagnosis and treatment of cardiovascular diseases. However, the acquisition of high-quality real-time cardiac MR (CMR) images is challenging as it requires a high frame rate and temporal resolution. To overcome this challenge, there have been recent efforts on several approaches including hardware-based improvements and image reconstruction techniques such as compressed sensing and parallel MRI. The use of parallel MRI techniques such as GRAPPA (Generalized Autocalibrating Partial Parallel Acquisition) is a promising approach for improving the temporal resolution of MRI and expanding its applications in clinical practice. However, the GRAPPA algorithm involves a significant amount of computation, particularly for high acceleration factors and large datasets. This can result in long reconstruction times, which can limit the ability to achieve real-time imaging or high frame rates. One solution to this challenge is to use specialized hardware i.e. field-programmable gate arrays (FPGAs). In this work, a novel 32-bit floating-point FPGA-based GRAPPA accelerator is proposed with an aim to reconstruct high-quality cardiac MR images at higher frame rates, making it well suited for real-time clinical applications. The proposed FPGA-based accelerator consists of custom-designed data processing units named as dedicated computational engines (DCEs) that allow for a continuous flow of data between the calibration and synthesis stages of GRAPPA reconstruction process. This greatly increases the throughput and reduces the latency of the overall proposed system. Moreover, a high-speed memory module (DDR4-SDRAM) is integrated with the proposed architecture to store the multi-coil MR data. An on-chip quad-core ARM Cortex-A53 processor is used to manage access control information required for data transfer between the DCEs and DDR4-SDRAM. The proposed accelerator is implemented on Xilinx Zynq UltraScale + MPSoC using high-level synthesis (HLS) and hardware descriptive language (HDL) with an aim to explore the trade-offs between the reconstruction time, resource utilization and design effort. Several experiments have been performed using in-vivo cardiac datasets i.e. 18-receiver coil and 30-receiver coil to evaluate the performance of the proposed accelerator. A comparison is performed with the contemporary CPU and GPU-based GRAPPA reconstruction methods in terms of reconstruction time, frames-per-second and reconstruction accuracy (RMSE and SNR). The results show that the proposed accelerator achieves speed-up factors up to 121× and 9× as compared to the contemporary CPU-based and GPU-based GRAPPA reconstruction methods, respectively. Moreover, it has been demonstrated that the proposed accelerator can achieve reconstruction rates of up to ∼27 frames-per-second while maintaining the visual quality of the reconstructed images.

Designing the nano-scale architecture of the air electrode for high-performance and robust reversible solid oxide cells

Herein, an innovative La0.6Sr0.4CoO3 (LSC) nanostructured air electrode, having superior catalytic activity and exceptional robustness against critical interfacial delamination-induced degradation, is reported. A ∼50 nm thin LSC air electrode decorated onto a porosity graded Gd0.1Ce0.9O2 backbone via ultrasonic-assisted infiltration showed significantly flourished ORR and OER kinetics with prolific electrochemical performance compared to the cell with conventional LSC air electrode. The SOC showed maximum power density of 2.24 W cm−2 in the fuel cell mode and maximum current density of 4.57 A cm−2 at an operating voltage of 1.6 V in the electrolysis mode at 750 °C. Results of the reversible cycling and galvanostatic stability tests indicate excellent durability, which is attributed to the elimination of detrimental O2 pressure evolved at the air electrode/electrolyte interface. Sited among the highest performances till date, this study provides a realization of a tremendously durable SOC design for the production of green hydrogen and electricity.

Design and Implementation of an Automatic Test and Verification System for SoC

With the development of semiconductor technology in recent years, the design of SoC has become more and more complex. [1]In order to ensure the correctness of chip design and the success rate of chip taping out, the verification test of SoC becomes more and more important. This paper designs an automated test and verification system based on STM32 and analog switch matrix chips. The system has high reusability, good scalability, convenient maintenance and automated test, and can improve the efficiency of test and verification, reduce the cost and shorten the development cycle of SoC.

Low Power Embedded SoC Design

Now a days all embedded processors are manufactured in such a way that it may consume low power to provide longer life to the system using various low power techniques like clock gating, data gating, variable frequency mechanism, variable voltage mechanism and variable threshold techniques. In this paper these techniques are implemented using VHDL language in Vivado and results are compared to identify the better one among all possible ones. There are various characteristics compared here are power consumption, number of look up tables and number of flip flops consumed.

Wireless Compact Neural Interface for Freely Moving Animal Subjects: A Review on Wireless Neural Interface SoC Designs

Wireless Compact Neural Interface for Freely Moving Animal Subjects: A Review on Wireless Neural Interface SoC Designs

Secured Data Transmission Over Insecure Networks-on-Chip by Modulating Inter-Packet Delays

As the network-on-chip (NoC) integrated into an SoC design can come from an untrusted third party, there is a growing risk that data integrity and security get compromised when supposedly sensitive data flows through such an untrusted NoC. We thus introduce a new method that can ensure secure and secret data transmission over such an untrusted NoC. Essentially, the proposed scheme relies on encoding binary data as delays between packets travelling across the source and destination pair. The maximum data transmission rate of this inter-packet-delay (IPD)-based communication channel can be determined from the analytical model developed in this article. To further improve the undetectability and robustness of the proposed data transmission scheme, a new block coding method and communication protocol are also proposed. Experimental results show that the proposed IPD-based method can achieve a packet error rate (PER) of as low as 0.3% and an effective throughput of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\boldsymbol {2.3\times 10^{5}}$ </tex-math></inline-formula> b/s, outperforming the methods of thermal covert channel, cache covert channel, and circuit-based encryption and, thus, is suitable for secure data transmission in unsecure systems.

Integrated Sensory Throughput and Traffic-Aware Arbiter for High Productive Multicore Architectures

The increasing demand for network and high-performance devices requires large data throughputs with minimal loss or repetition. Network on chips (NoC) provides excellent connectivity among multiple on-chip communicating devices with minimal loss compared with old bus systems. The motivation is to improve the throughput of the NoC that integrated on multicores for communication among cores by reducing the communication latency. The design of the arbiter in the crossbars switch of an NoC’s router has a vital role in judging the system’s speed and performance. Low latency and high-speed switching are possible with high performance and good switching equipment at the network level. One of the significant components in NoC under SoC design is the arbiter, which governs the system’s performance. Proper arbitrations can avoid network or traffic congestions like livelock and buffer waiting. The proposed work in this paper is to design an efficient and high productive arbiter for multicore chips, especially SoCs and CMPs. The proposed arbiter is showing good improvement in the throughput at higher data rates; an average of more than 10% throughput improvement is noticed at higher flit injection rates independent of the VCs implemented. Further, the critical delays are reduced to 15.84% with greater throughputs.

A Minimal Buffer Router with Level Encoded Dual Rail-Based Design of Network-on-Chip Architecture

Asynchronous NOCs are most prominent in present SOC designs, due to their low dynamic power consumption, modularity, heterogeneous nature, and robustness to the process variations. Though asynchronous designs are proved efficient over synchronous counterparts, they have some severe drawbacks when area and speed are considered, due to complex handshake control circuits which increase the static power loss. Quasidelay insensitive (QDI) class of asynchronous NOCs based on 2-phase encoding is proved beneficial for speed and throughput enhancement but with complex design. The work has introduced lightweight minimal buffer router based on LEDR encoding to design a low power, high speed with compact NOC architecture. Then, minimal buffer router with FSM-based arbiter and priority assigner block is designed to enhance the speed, power, and area. This proposed work achieves zero dynamic power consumption with a total power consumption of less than 0.082 W with a router latency of 0.8 ns.

Data-Driven Self-Optimizing Control With Parametric Programing Based Constraint Handling

AbstractSelf-optimizing control (SOC) aims to achieve near-optimal operation regardless of variation in disturbances. For constrained operation, the model-based SOC has been solved as an explicit model predictive control (MPC) problem, where the changes in active constraint sets under large variations in disturbance inputs can be determined via parametric programing. For constrained SOC design with historical data only, this paper presents an extended work for a data-driven method that Zhao et al. proposed (2022 “Global Self-Optimizing Control With Data-Driven Optimal Selection of Controlled Variables With Application to Chiller Plant”, ASME J. Dyn. Sys., Meas., Control., 144(2), p. 021008.) for obtaining global SOC solution. While this work remains to adopt the Koopman subspace model that has been used, the SOC-associated constrained optimization problem is solved by applying the multiparameter quadratic programing technique. The solutions consist of piecewise-affine control laws and active constraint sets that are determined via partitions of the disturbance space. The proposed approach is illustrated with a Modelica simulation model of a chilled-water plant, where minimizing the total power consumption is the economic objective. The results show that the proposed method yields the total power very close to that by an offline genetic algorithm-based global optimization procedure, and substantially better than a best-practice rule-based control strategy. The degree of constraint violations under high cooling load is also smaller with the solution of constrained SOC.

A Review on Design Implementation and Verification of AMBA AXI- 4 lite Protocol for SoC Integration

Abstract: The present modern bus protocols used for communication between different functional blocks on a System-on-Chip (Soc) designs face many different challenges among which complexity and communication management are the most important factors. These on-chip communications directly impact performance and functionality, hence depending on the application where the bus protocol is to be used, a perfect communication protocol is chosen. AMBA (Advanced Microcontroller Bus Architecture) provides various types of protocols to be used as IP, of which AXI4 (Advance Extensible Interface), is one of the widely used protocols for SoC designs. Out of its three different interconnect protocols: lite, stream and burst, AXI4-lite has the simplest architecture design that best suits to be used in applications where power, area and performance play a vital role. This paper briefs about using AMBA AXI4-lite bus protocol with more bus efficiency and performance in an SoC design for proper communication between various functional blocks present. The RTL is verified using UVM (Universal Verification Methodology) and various designing process is carried out using cadence tools.

Early SoCs Information Flow Policies Validation using SystemC-based Virtual Prototypes at the ESL

Virtual Prototypes (VPs) at the Electronic System Level (ESL) are being increasingly adopted by the semiconductor industry and play an important role in modernizing the System-on-Chips (SoCs) design flow to raise design productivity and reduce time-to-market constraints. Due to their early availability and significantly faster simulation speed in comparison to Register Transfer Level (RTL) designs, VPs are used as reference models for lower levels of abstraction. Leveraging VPs and extending their use-cases for early security validation are shown as a promising direction. As the cost of fixing any security flaws increases with the stage of development, VP-based security validation can significantly avoid costly iterations. In this paper, we present a novel VP-based dynamic information flow analysis approach at the ESL, consisting of three main phases which are run-time behavior extraction (in terms of transactions), transactions transformation, and security validation. The proposed approach empowers designers to validate the information flow policies of a given VP-based SoC against the most occurring security threat models which are information leakage (confidentiality) and unauthorized access to data in a memory (integrity). Experimental results including an extensive set of standard benchmarks and two real-world VP-based SoCs demonstrate the scalability and applicability of the proposed approach.

OPDB: A Scalable and Modular Design Benchmark

Progress in electronic design automation (EDA) has enabled us to manage the exponential growth of complexity in integrated circuits (ICs) allowed by Moore&#x2019;s Law, and translate it into performance improvements. Furthermore, as Moore&#x2019;s law slows down and with the collapse of Dennard scaling over the past decade, EDA tools become increasingly important in addressing inefficiencies in ICs. As new proposals and techniques are put forward to address the current and future issues of IC design, a concrete set of contemporary benchmarks needs to be used for their evaluation. Traditionally, EDA researchers have mainly relied on industry provided design benchmarks in evaluating the performance of their tools. However, due to their effort to maintain their competitive advantage, industry releases include older designs with limited information about the details of each design. This means that in multiple cases, new proposals are evaluated with significantly dated designs, often more than a decade old, especially in terms of scale. In this work, we describe OPDB: a scalable, modular, heterogeneous, and extensible design benchmark for the EDA community. OPDB leverages and extends the OpenPiton open-source, tile-based research infrastructure to create a surplus of design benchmarks that target different components. Due to the tiled nature of this architecture, OPDB benchmarks can be made arbitrarily large in order to evaluate the efficiency of EDA tools across different design scales and configurations. OPDB contains several accelerators enabling full SoC designs to be used as benchmarks for EDA tools.

Practical Application-Oriented Energy Management for a Plug-In Hybrid Electric Bus Using a Dynamic SOC Design Zone Plan Method

The main problem in current energy management is the ability of practical application. To address the problem, this paper proposes a reinforcement learning (RL)-based energy management by combining Tubule Q-learning and Pontryagin’s Minimum Principle (PMP) algorithms for a plug-in hybrid electric bus (PHEB). The main innovation distinguished from the existing energy management strategies is that a dynamic SOC design zone plan method is proposed. It is characterized by two aspects: ① a series of fixed locations are defined in the city bus route and a linear SOC reference trajectory is re-planned at fixed locations; ② a triangle zone will be re-planned based on the linear SOC reference trajectory. Additionally, a one-dimensional state space is also designed to ensure the real-time control. The off-line trainings demonstrate that the agent of the RL-based energy management can be well trained and has good generalization performance. The results of hardware in loop simulation (HIL) demonstrate that the trained energy management has good real-time performance, and its fuel consumption can be decreased by 12.92%, compared to a rule-based control strategy.

Test power and area optimized logic built-in self-test with higher fault coverage for automobile SoCs

With higher computerization in the automobile stream, the built-in self-test is essential for high quality and high-reliability SoCs. BIST is a self-testing method for the larger SoC designs. This paper presented a new logic BIST architecture with a new weighted pseudorandom TPG and a hybrid test point allocation method. The proposed architecture is optimized for the physical factors such as the test power consumption, the fault coverage, the WSA, and the area overhead during the scan-in testing phase. The proposed method initiated the sharing concept of flip-flops in the test gate strategies to optimize the area overhead. It also demonstrated the test point allocation enabled using the weighted patterns to enhance the fault coverage throughout the scan chains. The primary seeds are flipped and sorted into weighted patterns to obtain the transition delay faults as their complete fault coverage. Simulation works are examined in SilTerra 0.13 μm on Mentor Graphics IC design tool. Experimental results of the logic BIST architecture are executed, and the results are tabulated. The performance comparison of proposed logic BIST with the existing BIST architectures is also analyzed. Consequently, the proposed BIST is employed in the automobile SoC as an application. The ADAS automobile SoC scan circuits were tested in this paper for their self-testing phenomenon. The tabulated results for the physical factors showed that valuable improvements could be accomplished using the proposed BIST compared with the existing authors.

Data Mining Software Tools and Methodologies for VLSI Design

Modern VLSI design process employs numerous EDA tools to produce large-size report files. It is time consuming as well as the possibility to miss some violations from EDA report files. We developed two data mining software tools targeting for the timing, noise and power grid analysis report files in one high-performance SOC design project. The software extracts, sorts and displays the key information from EDA report files into HTML forms, which can be viewed by designers using the web browser. Organization of EDA report files, configure files, program execution flows and output HTML forms are described for the developed data mining software tools.

An energy efficient synthesis flow for application specific SoC design

Multiple Supply Voltage (MSV) is a known design technique to deal with the power and thermal issues of Multi Processor System on Chips (MPSoCs). In this paper, an MSV driven synthesis flow is proposed in four phases for the design of application-specific MPSoCs. The first phase conducts the core-to-router allocation concerning the operating voltages of cores as well as the bandwidth/latency requirements of the data flowing between the cores. The second phase coordinates voltages of cores connected to the same router. The third phase refines the power delivery network using our proposed voltage-aware hierarchical floorplanning algorithm. Finally, router-to-router connection and path allocation are done by the use of existing methods in the last phase. For the first time, we perform the core to router allocation phase before the voltage islanding phase to find the highest number of design solutions satisfying the set of given constraints; this in turn, improves the flexibility and efficiency of our synthesis process. Exhaustive experimental evaluations have been done on real-world benchmarks. Results confirm achieving 90% more design solutions (to conduct a wiser design space exploration) and an average of 93% Energy Delay Product (EDP) improvement as compared to the existing synthesis approaches.

Aldec Targets ASIC &amp; SoC Designs

Aldec Targets ASIC &amp; SoC Designs

Voltage tunable current MODE KHN filter based on current differencing transconductance amplifier (CDTA)

The era of SoC design has great dependency on CMOS circuits owing to its low power and high reliability which could contribute in the effective circuit designing. Here, a unique approach for the designing of voltage tunable current differencing transconductance amplifier (CDTA) is reported for the realization of Kerwin–Huelsman–Newcomb (KHN) filter. The proposed design has been simulated by using Cadence Virtuoso simulation tool with 0.18 [Formula: see text]m technology parameters. This design is based on input voltage-based gain and frequency of operation tuning approach. In this reported design of filter, cutoff frequency can be tailored by input voltage instead of input current. This relaxes the need for the iterative circuit modifications to work in a particular frequency range. Thus, the reported CDTA design is expected to be robust and offers higher design flexibility as there is now no need of iterative designing and calibration in this approach. This also exhibits retained area requirement as per the current state of the art for the KHN filters. Further, the performance of designed CDTA-based KHN filter has also been verified with the existing KHN filters.

Heterogeneity-Aware Scheduling on SoCs for Autonomous Vehicles

Fully autonomous vehicles (AVs) must meet stringent real-time performance and safety-criticality constraints of multiple applications simultaneously in highly dynamic environmental conditions. To enable such a system, carefully selected accelerators and general-purpose cores on Systems-on-Chips (SoCs) are required. However, schedulers that are agnostic to this heterogeneity lead to inefficient utilization of hardware resources and increase the time to complete the AV's mission. As a solution, our letter proposes a heterogeneity-aware, multi-level scheduler called HetSched. HetSched leverages run-time information about the underlying heterogeneous SoC, along with the applications’ real-time constraints to improve an AV's mission time. Our evaluation demonstrates a reduction in mission time of 2.0-4.8×, when compared against state-of-the-art (SOTA) schedulers. Furthermore, when used as part of an SoC design space exploration loop, in comparison to the SOTA schedulers, HetSched reduces the number of accelerators required by an SoC to safely complete the AV's mission by 1.9× on average.